Inventor
Jason M. Norman
Inventor
Essex Junction, VT, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing50%
G01RMeasuring electric variables14%
H04BTransmission9%
H04LTransmission of digital information, e.g. telegraphic communication9%
G01KMeasuring temperature5%
G02BOptical elements, systems or apparatus5%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices5%
H10DInorganic electric semiconductor devices5%
PatentTitleYear
10,754,790Translation of virtual addresses to physical addresses using translation lookaside buffer information20208,539,404'Functional simulation redundancy reduction by state comparison and pruning'20138,347,019'Structure for hardware assisted bus state transition circuit using content addressable memories'20137,898,286'Critical path redundant logic for mitigation of hardware across chip variation'20117,865,789'System and method for system-on-chip interconnect verification'20117,823,107'Transition balancing for noise reduction/Di/Dt reduction during design, synthesis, and physical design'20107,743,270'Assigning clock arrival time for noise reduction'20107,643,591'Transition balancing for noise reduction /Di/Dt reduction during design, synthesis, and physical design'20107,519,941'Method of manufacturing integrated circuits using pre-made and pre-qualified exposure masks for selected blocks of circuitry'20097,313,738'System and method for system-on-chip interconnect verification'20077,308,663'Circuit design verification using checkpointing'20077,286,770'Fiber optic transmission lines on an SOC'20077,275,011'Method and apparatus for monitoring integrated circuit temperature through deterministic path delays'20077,248,838'Wireless communication system within a system on a chip'20077,139,881'Semiconductor device comprising a plurality of memory structures'20067,103,320'Wireless communication system within a system on a chip'20067,091,743'Data acknowledgment using impedance mismatching'20067,085,993'System and method for correcting timing signals in integrated circuits'20066,934,656'Auto-linking of function logic state with testcase regression list'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2013Patents assigned to IBM (18)· patent assignee history
2005–2007Based in South Burlington, VT, US· patent location history
2006Based in Burlington, VT, US· patent location history
2007–2013Based in Essex Junction, VT, US· patent location history
2013Patents assigned to BUETI SERAFINO (1)· patent assignee history
2013Patents assigned to CRAIG JESSE E (1)· patent assignee history
2013Patents assigned to GOODNOW KENNETH JOSEPH (1)· patent assignee history
2013Patents assigned to LEONARD TODD EDWIN (1)· patent assignee history
2020Based in Cary, NC, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 2005–2013 |
| BUETI SERAFINO | 1 | 2013 |
| CRAIG JESSE E | 1 | 2013 |
| GOODNOW KENNETH JOSEPH | 1 | 2013 |
| LEONARD TODD EDWIN | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 11 | 2007–2013 |
| South Burlington, VT, US | 6 | 2005–2007 |
| Cary, NC, US | 1 | 2020 |
| Burlington, VT, US | 1 | 2006 |