Inventor
Kenichi Koyanagi
Inventor
Tokyo, JP
Overview
Patents· 25 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices25%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1020%
C23CCoating metallic material13%
H10BElectronic memory devices13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h107%
B25JManipulators3%
G05BControl or regulating systems in general3%
H01GCapacitors3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
C03CChemical composition of glasses, glazes or vitreous enamels2%
PatentTitleYear
9,178,006'Methods to improve electrical performance of ZrO2 based high-K dielectric materials for DRAM applications'20158,880,217'Picking system'20148,880,216'Picking system'20148,606,400'Robot system'20138,574,998'Leakage reduction in DRAM MIM capacitors'20138,546,236'High performance dielectric stack for DRAM capacitor'20138,541,283'High performance dielectric stack for DRAM capacitor'20138,476,141'High performance dielectric stack for DRAM capacitor'20138,415,227'High performance dielectric stack for DRAM capacitor'20138,277,891'Method for suppressing particle generation during semiconductor manufacturing'20127,771,535'Semiconductor manufacturing apparatus'20107,763,500'Method for manufacturing semiconductor storage device comprising a slow cooling step'20107,741,173'Method for forming a metal oxide film'20107,576,016'Process for manufacturing semiconductor device'20097,303,973'ALD process for capacitor dielectric'20077,256,144'Method for forming a metal oxide film'20077,224,016'Memory with memory cells that include a MIM type capacitor with a lower electrode made for reduced resistance at an interface with a metal film'20076,939,760'Method for semiconductor device manufacturing to include multistage chemical vapor deposition of material oxide film'20056,509,200'Method of appraising a dielectric film, method of calibrating temperature of a heat treatment device, and method of fabricating a semiconductor memory device'20036,346,302'High density plasma enhanced chemical vapor deposition method'20026,191,002'Method of forming trench isolation structure'20016,187,693'Heat treatment of a tantalum oxide film'20016,033,990'Method for manufacturing a multilevel interconnection structure'20006,005,291'Semiconductor device and process for production thereof'19995,891,234'Spin on glass material and method for forming a semiconductor device by using improved spin on glass material'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2003Patents assigned to NEC CORP (7)· patent assignee history
1999–2012Based in Tokyo, JP· patent location history
2005–2015Patents assigned to ELPIDA MEMORY INC (12)· patent assignee history
2012–2014Patents assigned to KOYANAGI KENICHI (6)· patent assignee history
2013–2015Patents assigned to INTERMOLECULAR INC (6)· patent assignee history
2013–2014Patents assigned to HASHIGUCHI YUKIO (3)· patent assignee history
2013–2015Based in Higashihiroshima, JP· patent location history
2013–2014Based in Kitakyushu, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ELPIDA MEMORY INC | 12 | 2005–2015 |
| NEC CORP | 7 | 1999–2003 |
| INTERMOLECULAR INC | 6 | 2013–2015 |
| KOYANAGI KENICHIself | 6 | 2012–2014 |
| HASHIGUCHI YUKIO | 3 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokyo, JP | 16 | 1999–2012 |
| Higashihiroshima, JP | 6 | 2013–2015 |
| Kitakyushu, JP | 3 | 2013–2014 |