Inventor
Katsuhiko Ichinose
Inventor
Tokorozawa, JP
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices36%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1031%
H01LSemiconductor devices8%
H10BElectronic memory devices8%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
G01NInvestigating or analysing materials by determining their chemical or physical properties5%
C23CCoating metallic material3%
G06TImage data processing or generation, in general3%
PatentTitleYear
9,978,869P-channel transistor having an increased channel mobility due to a compressive stress-inducing gate electrode20189,412,669'Semiconductor device and a method of manufacturing the same'20168,995,748'Defect image processing apparatus, defect image processing method, semiconductor defect classifying apparatus, and semiconductor defect classifying method'20158,963,250'Semiconductor device including a film for applying stress to a channel formation region to increase current flow'20158,595,666'Semiconductor defect classifying method, semiconductor defect classifying apparatus, and semiconductor defect classifying program'20137,705,402'Semiconductor device including a nitride containing film to generate stress for improving current driving capacity of a field effect transistor'20107,414,293'Structure and method of applying localized stresses to the channels of PFET and NFET transistors for improved performance'20087,411,253'CMOS transistors using gate electrodes to increase channel mobilities by inducing localized channel stress'20087,163,886'Semiconductor integrated circuit device and process for manufacturing the same'20077,115,954'Semiconductor device including stress inducing films formed over n-channel and p-channel field effect transistors and a method of manufacturing the same'20066,982,465'Semiconductor device with CMOS-field-effect transistors having improved drain current characteristics'20066,933,564'Semiconductor integrated circuit device and method of manufacturing the same'20056,905,982'Method of manufacturing a semiconductor integrated circuit device'20056,847,093'Semiconductor integrated circuit device'20056,806,128'Semiconductor integrated circuit device and a method of manufacturing the same'20046,706,582'Semiconductor integrated circuit device and method of manufacturing the same'20046,613,634'Method of manufacturing a semiconductor device using oblique ion injection'2003Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2003–2007Based in Ome, JP· patent location history
2004–2010Patents assigned to RENESAS TECH CORP (10)· patent assignee history
2005–2016Based in Tokorozawa, JP· patent location history
2013–2015Patents assigned to ICHINOSE KATSUHIKO (3)· patent assignee history
2013–2015Patents assigned to HITACHI HIGH TECH CORP (2)· patent assignee history
2013–2015Patents assigned to ISHIKAWA TAMAO (2)· patent assignee history
2015–2018Patents assigned to RENESAS ELECTRONICS CORP (3)· patent assignee history
2018Based in Tokyo, JP· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RENESAS TECH CORP | 10 | 2004–2010 |
| ICHINOSE KATSUHIKOself | 3 | 2013–2015 |
| RENESAS ELECTRONICS CORP | 3 | 2015–2018 |
| HITACHI HIGH TECH CORP | 2 | 2013–2015 |
| ISHIKAWA TAMAO | 2 | 2013–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Tokorozawa, JP | 10 | 2005–2016 |
| Ome, JP | 6 | 2003–2007 |
| Tokyo, JP | 1 | 2018 |