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Inventor

Wah Kit Loh

Inventor
Richardson, TX, US

Overview

43→
Patents
1992–2017
Patent span
Physics
Primary field (CPC G)

Patents· 43 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G11Cprimary
G11CStatic stores55%
H10BElectronic memory devices8%
G06FElectric digital data processing7%
H10DInorganic electric semiconductor devices7%
G01RMeasuring electric variables4%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G05FSystems for regulating electric or magnetic variables3%
Y02PClimate change mitigation technologies in the production or processing of goods3%
H01LSemiconductor devices1%
H03KPulse technique1%
PatentTitleYear
9,805,788'Array power supply-based screening of static random access memory cells for bias temperature instability'20179,576,643'Array power supply-based screening of static random access memory cells for bias temperature instability'20179,576,621'Read-current and word line delay path tracking for sense amplifier enable timing'20179,472,268'SRAM with buffered-read bit cells and its testing'20169,466,356'Array power supply-based screening of static random access memory cells for bias temperature instability'20169,455,021'Array power supply-based screening of static random access memory cells for bias temperature instability'20169,412,437'SRAM with buffered-read bit cells and its testing'20169,208,902'Bitline leakage detection in memories'20159,208,899'Universal test structures based SRAM on-chip parametric test module and methods of operating and testing'20159,208,832'Functional screening of static random access memories using an array bias voltage'20159,093,315'CMOS process to improve SRAM yield'20158,971,138'Method of screening static random access memory cells for positive bias temperature instability'20158,755,237'SRAM power reduction through selective programming'20148,716,808'Static random-access memory cell array with deep well regions'20148,654,562'Static random access memory cell with single-sided buffer and asymmetric construction'20148,603,875'CMOS process to improve SRAM yield'20138,560,931'Low power retention random access memory with error correction on wake-up'20138,542,545'Repairing soft failures in memory cells in SRAM arrays'20138,526,253'Method of screening static random access memories for pass transistor defects'20138,472,228'Array-based integrated circuit with reduced proximity effects'20138,472,229'Array-based integrated circuit with reduced proximity effects'20138,467,233'Asymmetric static random access memory cell with dual stress liner'20138,437,213'Characterization of bits in a functional memory'20138,432,760'Method of screening static random access memories for unstable memory cells'20138,379,467'Structure and methods for measuring margins in an SRAM bit'20138,233,341'Method and structure for SRAM cell trip voltage measurement'20128,228,749'Margin testing of static random access memory cells'20128,174,914'Method and structure for SRAM Vmin/Vmax measurement'20128,139,431'Structure and methods for measuring margins in an SRAM bit'20127,924,640'Method for memory cell characterization using universal structure'20117,821,816'Method for constructing Shmoo plots for SRAMs'20107,385,864'SRAM static noise margin test structure suitable for on chip parametric measurements'20087,324,391'Method for determining and classifying SRAM bit fail modes suitable for production test implementation and real time feedback'20087,216,272'Method for reducing SRAM test time by applying power-up state knowledge'20076,281,760'On-chip temperature sensor and oscillator for reduced self-refresh current for dynamic random access memory'20016,239,650'Low power substrate bias circuit'20015,959,912'ROM embedded mask release number for built-in self-test'19995,923,599'Apparatus and method for subarray testing in dynamic random access memories using a built-in-self-test unit'19995,844,853'Memory regulator control method with flexibility for a wide change in supply voltage'19985,309,446'Test validation method for a semiconductor memory device'19945,220,534'Substrate bias generator system'19935,200,364'Packaged integrated circuit with encapsulated electronic devices'19935,115,298'Packaged integrated circuit with encapsulated electronic devices'1992

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1992–2017Patents assigned to TEXAS INSTRUMENTS INC (43)· patent assignee history
1992–2017Based in Richardson, TX, US· patent location history
1993Based in Houston, TX, US· patent location history
2012–2016Patents assigned to LOH WAH KIT (18)· patent assignee history
2012–2016Patents assigned to DENG XIAOWEI (13)· patent assignee history
2012–2013Patents assigned to HOUSTON THEODORE W (3)· patent assignee history
2013–2015Patents assigned to SESHADRI ANAND (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
TEXAS INSTRUMENTS INC431992–2017
LOH WAH KITself182012–2016
DENG XIAOWEI132012–2016
SESHADRI ANAND42013–2015
HOUSTON THEODORE W32012–2013
Locations
LocationPatentsSpan
Richardson, Texas, US421992–2017
Houston, Texas, US11993