Inventor
Gilbert M. Wolrich
Inventor
Framingham, MA, US
Overview
Patents· 263 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing56%
H04LTransmission of digital information, e.g. telegraphic communication24%
H03MCoding8%
G09CCiphering or deciphering apparatus for cryptographic or other purposes involving the need for secrecy5%
G11CStatic stores3%
H04WWireless communication networks1%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests1%
G06KGraphical data reading1%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use1%
F02BInternal-combustion piston engines0%
PatentTitleYear
11,106,461Rotate instructions that complete execution either without writing or reading flags202111,080,045Addition instructions with independent carry chains202110,911,222Instructions processors, methods, and systems to process secure hash algorithms202110,778,425Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality202010,725,779Method and apparatus to process SHA-2 secure hashing algorithm202010,691,458Method and apparatus to process KECCAK secure hashing algorithm202010,686,591Instruction and logic to provide SIMD secure hashing round slice functionality202010,684,855Method and apparatus for performing a shift and exclusive or operation in a single instruction202010,649,774Multiplication instruction for which execution completes without writing a carry flag202010,592,245Instructions and logic to provide SIMD SM3 cryptographic hashing functionality202010,581,594Instructions processors, methods, and systems to process secure hash algorithms202010,503,510SM3 hash function message expansion processors, methods, systems, and instructions201910,379,853Sliding window encoding methods for executing vector compare instructions to write distance and match information to different sections of the same register201910,331,450Method and apparatus to process SHA-2 secure hashing algorithm201910,331,451Method and apparatus to process SHA-2 secure hashing algorithm201910,296,467Securing writes to memory modules having memory controllers201910,218,739Filter for network intrusion and virus detection201910,203,934Parallell processing of a single data buffer201910,198,248Parallel processing of a single data buffer201910,169,073Hardware accelerators and methods for stateful compression and decompression operations201910,158,484Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality201810,158,376Techniques to accelerate lossless compression201810,152,326Method and apparatus to process SHA-2 secure hashing algorithm201810,148,428Instruction and logic to provide SIMD secure hashing round slice functionality201810,146,544Method and apparatus to process SHA-2 secure hashing algorithm201810,140,046Supporting data compression using match scoring201810,127,042Method and apparatus to process SHA-2 secure hashing algorithm201810,108,805Method and apparatus to process SHA-2 secure hashing algorithm201810,102,215Apparatus for hardware implementation of lossless data compression201810,089,500Secure modular exponentiation processors, methods, systems, and instructions201810,069,512Systems, methods, and apparatuses for decompression using hardware and software201810,042,639Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction201810,037,210Apparatus and method for vector instructions for large integer arithmetic201810,009,172Instructions processors, methods, and systems to process secure hash algorithms20189,990,201Multiplication instruction for which execution completes without writing a carry flag20189,960,917Matrix multiply accumulate instruction20189,940,131Rotate instructions that complete execution either without writing or reading flags20189,940,130Rotate instructions that complete execution either without writing or reading flags20189,916,160'Rotate instructions that complete execution either without writing or reading flags'20189,917,689'Generating multiple secure hashes from a single data buffer'20189,912,481'Method and apparatus for efficiently executing hash operations'20189,910,790'Using a memory address to form a tweak key to use to encrypt and decrypt data'20189,900,770'Instruction for accelerating SNOW 3G wireless security algorithm'20189,898,300'Instruction for fast ZUC algorithm processing'20189,871,535'Heterogeneous compression architecture for optimized compression ratio'20189,830,284Memory mapping in a processor having multiple programmable units20179,830,285Memory mapping in a processor having multiple programmable units20179,824,037'Memory mapping in a processor having multiple programmable units'20179,824,038'Memory mapping in a processor having multiple programmable units'20179,772,845'Method and apparatus to process KECCAK secure hashing algorithm'20179,768,802'Look-ahead hash chain matching for data compression'20179,747,105'Method and apparatus for performing a shift and exclusive or operation in a single instruction'20179,740,484'Processor-based apparatus and method for processing bit streams using bit-oriented instructions through byte-oriented storage'20179,733,858'Supporting data compression using match scoring'20179,690,488'Data compression using accelerator with multiple search engines'20179,658,854'Instructions and logic to provide SIMD SM3 cryptographic hashing functionality'20179,632,782'Method and apparatus to process SHA-2 secure hashing algorithm'20179,614,544'Systems, methods, and apparatuses for decompression using hardware and software'20179,594,695'Supporting data compression using match scoring'20179,584,155'Look-ahead hash chain matching for data compression'20179,569,210'Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm'20179,542,561'Instructions processors, methods, and systems to process secure hash algorithms'20179,535,706'Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction'20179,537,504'Heterogeneous compression architecture for optimized compression ratio'20179,503,256'SMS4 acceleration hardware'20169,501,281'Method and apparatus for performing a shift and exclusive or operation in a single instruction'20169,495,166'Method and apparatus for performing a shift and exclusive or operation in a single instruction'20169,495,165'Method and apparatus for performing a shift and exclusive or operation in a single instruction'20169,490,971'Instruction for fast ZUC algorithm processing'20169,489,199'Vector compare instructions for sliding window encoding'20169,473,168'Systems, methods, and apparatuses for compression using hardware and software'20169,467,279'Instructions and logic to provide SIMD SM4 cryptographic block cipher functionality'20169,436,435'Apparatus and method for vector instructions for large integer arithmetic'20169,425,953'Generating multiple secure hashes from a single data buffer'20169,419,647'Partitioned data compression using accelerator'20169,419,648'Supporting data compression using match scoring'20169,419,792'Instruction for accelerating SNOW 3G wireless security algorithm'20169,405,537'Apparatus and method of execution unit for calculating multiple rounds of a skein hashing algorithm'20169,361,106'SMS4 acceleration processors, methods, systems, and instructions'20169,292,297'Method and apparatus to process 4-operand SIMD integer multiply-accumulate instruction'20169,294,123'Apparatus and method to accelerate compression and decompression operations'20169,292,548'Digest generation'20169,270,460'Instructions to perform JH cryptographic hashing in a 256 bit data path'20169,270,698'Filter for network intrusion and virus detection'20169,251,377'Instructions processors, methods, and systems to process secure hash algorithms'20169,251,374'Instructions to perform JH cryptographic hashing'20169,235,414'SIMD integer multiply-accumulate instruction for multi-precision arithmetic'20169,203,887'Bitstream processing using coalesced buffers and delayed matching and enhanced memory writes'20159,164,762'Rotate instructions that complete execution without reading carry flag'20159,128,818'Memory mapping in a processor having multiple programmable units'20159,128,698'Systems, apparatuses, and methods for performing rotate and XOR in response to a single instruction'20159,100,184'Instructions processors, methods, and systems to process BLAKE secure hashing algorithm'20159,092,645'Efficient multiplication, exponentiation and modular reduction implementations'20159,052,985'Method and apparatus for efficient programmable cyclic redundancy check (CRC)'20159,047,082'Instruction-set architecture for programmable Cyclic Redundancy Check (CRC) computations'20159,027,104'Instructions processors, methods, and systems to process secure hash algorithms'20158,953,785'Instruction set for SKEIN256 SHA3 algorithm on a 128-bit processor'20158,954,754'Method and apparatus to process SHA-1 secure hashing algorithm'20158,947,270'Apparatus and method to accelerate compression and decompression operations'20158,929,539'Instructions to perform Groestl hashing'20158,930,681'Enhancing performance by instruction interleaving and/or concurrent processing of multiple buffers'20158,924,741'Instruction and logic to provide SIMD secure hashing round slice functionality'20148,874,933'Instruction set for SHA1 round processing on 128-bit data paths'20148,838,997'Instruction set for message scheduling of SHA256 algorithm'20148,781,110'Unified system architecture for elliptic-curve cryptography'20148,738,893'Add instructions to add three source operands'20148,738,886'Memory mapping in a processor having multiple programmable units'20148,732,548'Instruction-set architecture for programmable cyclic redundancy check (CRC) computations'20148,689,078'Determining a message residue'20148,549,264'Add instructions to add three source operands'20138,520,845'Method and apparatus for expansion key generation for block ciphers'20138,504,807'Rotate instructions that complete execution without reading carry flag'20138,484,147'Pattern matching'20138,464,125'Instruction-set architecture for programmable cyclic redundancy check (CRC) computations'20138,392,494'Method and apparatus for performing efficient side-channel attack resistant reduction using montgomery or barrett reduction'20138,391,475'Method and apparatus for advanced encryption standard (AES) block cipher'20138,380,767'Polynomial-basis to normal-basis transformation for binary Galois-Fields GF(2m)'20138,380,923'Queue arrays in network devices'20138,380,777'Normal-basis to canonical-basis transformation for binary galois-fields GF(2m)'20138,363,828'Diffusion and cryptographic-related operations'20138,346,839'Efficient advanced encryption standard (AES) datapath using hybrid rijndael S-box'20138,325,069'System, method, and apparatus for a scalable processor architecture for a variety of string processing applications'20128,316,191'Memory controllers for processor having multiple programmable units'20128,312,363'Residue generation'20128,301,680'Apparatus and method to compute reciprocal approximations'20128,271,570'Unified integer/galois field (2m) multiplier architecture for elliptic-curve crytpography'20128,189,792'Method and apparatus for performing cryptographic operations'20128,073,892'Cryptographic system, method and multiplier'20118,065,678'Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor'20118,041,945'Method and apparatus for performing an authentication after cipher operation in a network processor'20118,042,025'Determining a message residue'20118,020,142'Hardware accelerator'20118,005,210'Modulus scaling for elliptic-curve cryptography'20117,991,983'Register set used in multithreaded parallel processor architecture'20117,986,779'Efficient elliptic-curve cryptography based on primality of the order of the ECC-group'20117,978,846'Scale-invariant barrett reduction for elliptic-curve cyrptography'20117,953,221'Method for processing multiple operations'20117,925,011'Method for simultaneous modular exponentiations'20117,912,886'Configurable exponent FIFO'20117,900,022'Programmable processing unit with an input buffer and output buffer configured to exclusively exchange data with either a shared memory logic or a multiplier based upon a mode instruction'20117,895,239'Queue arrays in network devices'20117,886,214'Determining a message residue'20117,872,598'Accelerated decompression'20117,853,951'Lock sequencing to reorder and grant lock requests from multiple program threads'2010RE041849'Parallel multi-threaded processing'20107,797,612'Storage accelerator'20107,769,026'Efficient sort scheme for a hierarchical scheduler'20107,751,402'Method and apparatus for gigabit packet assignment for multithreaded packet processing'20107,743,235'Processor having a dedicated hash unit integrated within'20107,738,657'System and method for multi-precision division'20107,725,624'System and method for cryptography processing units and multiplier'20107,681,018'Method and apparatus for providing large register address space while maximizing cycletime performance for a multi-threaded register file set'20107,664,915'High performance raid-6 system architecture with pattern matching'20107,620,702'Providing real-time control data for a network processor'20097,610,451'Data transfer mechanism using unidirectional pull bus and push bus'20097,607,068'Apparatus and method for generating a Galois-field syndrome'20097,555,630'Method and apparatus to provide efficient communication between multi-threaded processing elements in a processor unit'20097,554,908'Techniques to manage flow control'20097,546,444'Register set used in multithreaded parallel processor architecture'20097,543,142'Method and apparatus for performing an authentication after cipher operation in a network processor'20097,539,718'Method and apparatus for performing Montgomery multiplications'20097,529,924'Method and apparatus for aligning ciphered data'20097,512,945'Method and apparatus for scheduling the processing of commands for execution by cryptographic algorithm cores in a programmable network processor'20097,505,410'Method and apparatus to support efficient check-point and role-back operations for flow-controlled queues in network devices'20097,487,505'Multithreaded microprocessor with register allocation based on number of active threads'20097,475,229'Executing instruction for processing by ALU accessing different scope of variables using scope index automatically changed upon procedure call and exit'20097,467,256'Processor having content addressable memory for block-based queue structures'20087,460,544'Flexible mesh structure for hierarchical scheduling'20087,443,836'Processing a data packet'20087,441,245'Phasing for a multi-threaded network processor'20087,437,724'Registers for data transfers'20087,434,221'Multi-threaded sequenced receive for fast network port stream of packets'20087,433,307'Flow control in a network environment'20087,426,215'Method and apparatus for scheduling packets'20087,424,579'Memory controller for processor having multiple multithreaded programmable units'20087,421,572'Branch instruction for processor with branching dependent on a specified bit in a register'20087,418,540'Memory controller with command queue look-ahead'20087,418,543'Processor having content addressable memory with command ordering'20087,418,571'Memory interleaving'20087,412,584'Data alignment micro-architecture systems and methods'20087,376,950'Signal aggregation'20087,373,514'High-performance hashing system'20087,366,865'Enqueueing entries in a packet queue referencing packets'20087,336,606'Circular link list scheduling'20087,337,275'Free list and ring data structure management'20087,328,289'Communication between processors'20087,325,099'Method and apparatus to enable DRAM to support low-latency access via vertical caching'20087,305,500'Sram controller for parallel processor architecture including a read queue and an order queue for handling requests'20077,302,549'Processing packet sequence using same function set pipelined multiple threads spanning over multiple processing engines and having exclusive data access'20077,277,990'Method and apparatus providing efficient queue descriptor memory access'20077,269,179'Control mechanisms for enqueue and dequeue operations in a pipelined network processor'20077,246,197'Software controlled content addressable memory in a general purpose execution datapath'20077,240,164'Folding for a multi-threaded network processor'20077,225,281'Multiprocessor infrastructure for providing flexible bandwidth allocation via multiple instantiations of separate data buses, control buses and support mechanisms'20077,216,204'Mechanism for providing early coherency detection to enable high performance memory updates in a latency sensitive multithreaded environment'20077,191,309'Double shift instruction for micro engine used in multithreaded parallel processor architecture'20077,191,321'Microengine for parallel processor architecture'20077,181,568'Content addressable memory to identify subtag matches'20077,181,573'Queue array caching in network devices'20077,181,594'Context pipelines'20077,158,964'Queue management'20077,149,226'Processing data packets'20067,111,296'Thread signaling in multi-threaded processor'20067,107,413'Write queue descriptor count instruction for high speed queuing'20067,082,104'Network device switch'20067,043,516'Reduction of add-pipe logic by operand offset shift'20067,023,844'Scalable switching fabric'20066,983,350'SDRAM controller for parallel processor architecture'20066,976,095'Port blocking technique for maintaining receive packet ordering for a multiple ethernet port switch'20056,973,550'Memory access control'20056,952,824'Multi-threaded sequenced receive for fast network port stream of packets'20056,941,438'Memory interleaving'20056,934,951'Parallel processor with functional pipeline providing programming engines by supporting multiple contexts and critical section'20056,895,457'Bus interface with a first-in-first-out memory'20056,876,561'Scratchpad memory'20056,868,476'Software controlled content addressable memory in a general purpose execution datapath'20056,823,438'Method for memory allocation and management using push/pop apparatus'20046,792,488'Communication between processors'20046,779,084'Enqueue operations for multi-buffer packets'20046,738,831'Command ordering'20046,728,845'SRAM controller for parallel processor architecture and method for controlling access to a RAM using read and read/write queues'20046,694,380'Mapping requests from a processing unit that uses memory-mapped input-output space'20046,687,246'Scalable switching fabric'20046,681,300'Read lock miss control and queue management'20046,668,317'Microengine for parallel processor architecture'20036,668,311'Method for memory allocation and management using push/pop apparatus'20036,667,920'Scratchpad memory'20036,661,794'Method and apparatus for gigabit packet assignment for multithreaded packet processing'20036,631,430'Optimizations to receive packet status from fifo bus'20036,631,462'Memory shared between processing threads'20036,629,237'Solving parallel problems employing hardware multi-threading in a parallel processing environment'20036,625,654'Thread signaling in multi-threaded network processor'20036,606,704'Parallel multithreaded processor with plural microengines executing multiple threads each microengine having loadable microcode'20036,587,906'Parallel multi-threaded processing'20036,584,522'Communication between processors'20036,577,542'Scratchpad memory'20036,560,667'Handling contiguous memory references in a multi-queue system'20036,532,509'Arbitrating command requests in a parallel multi-threaded processing system'20036,463,072'Method and apparatus for sharing access to a bus'20026,427,196'SRAM controller for parallel processor architecture including address and command queue and arbiter'20026,324,624'Read lock miss control and queue management'20016,307,789'Scratchpad memory'20016,160,809'Distributed packet data with centralized snooping and header processing router'20006,131,107'Fast determination of carry inputs from lower order product for radis-8 odd/even multiplier array'20006,101,516'Normalization shift prediction independent of operand subtraction'20006,018,756'Reduced-latency floating-point pipeline using normalization shifts of both operands'20005,968,153'Mechanism for high bandwidth DMA transfers in a PCI environment'19995,889,692'Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array'19995,884,050'Mechanism for high bandwidth DMA transfers in a PCI environment'19995,867,407'Normalization shift prediction independent of operand substraction'19995,825,679'Fast sign extend for multiplier array sums and carrys'19985,811,998'State machine phase lock loop'19985,809,320'High-performance multi-processor having floating point unit'19985,796,976'Temporary storage having entries smaller than memory bus'19985,742,537'Fast determination of floating point sticky bit from input operands'19985,729,485'Fast determination of carry inputs from lower order product for radix-8 odd/even multiplier array'19985,726,927'Multiply pipe round adder'19985,694,350'Rounding adder for floating point processor'19975,627,773'Floating point unit data path alignment'19975,418,973'Digital computer system with cache controller coordinating both vector and scalar operations'19954,887,232'Apparatus and method for performing a shift operation in a multiplier array circuit'19894,811,272'Apparatus and method for an extended arithmetic logic unit for expediting selected floating point operations'19894,623,981'ALU with carry length detection'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–2021Based in Framingham, MA, US· patent location history
2001–2021Patents assigned to INTEL CORP (240)· patent assignee history
2003Based in Fermingham, MA, US· patent location history
2007–2021Patents assigned to WOLRICH GILBERT M (40)· patent assignee history
2011–2021Patents assigned to GOPAL VINODH (48)· patent assignee history
2011–2021Patents assigned to FEGHALI WAJDI K (36)· patent assignee history
2012–2021Patents assigned to OZTURK ERDINC (31)· patent assignee history
2015–2017Based in Farmingham, MA, US· patent location history
2021Based in Fromingham, MA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 240 | 2001–2021 |
| GOPAL VINODH | 48 | 2011–2021 |
| WOLRICH GILBERT Mself | 40 | 2007–2021 |
| FEGHALI WAJDI K | 36 | 2011–2021 |
| OZTURK ERDINC | 31 | 2012–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Framingham, Massachusetts, US | 256 | 1986–2021 |
| Farmingham, Massachusetts, US | 5 | 2015–2017 |
| Fromingham, Massachusetts, US | 1 | 2021 |
| Fermingham, Massachusetts, US | 1 | 2003 |