Inventor
JUI-CHE TSAI
Inventor
TW
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores41%
H01LSemiconductor devices10%
H03KPulse technique10%
H10DInorganic electric semiconductor devices10%
G06FElectric digital data processing8%
H04LTransmission of digital information, e.g. telegraphic communication8%
G06NComputing arrangements based on specific computational models6%
H10BElectronic memory devices4%
G06TImage data processing or generation, in general2%
G06VImage or video recognition or understanding2%
PatentTitleYear
12,445,312I/O circuit design for SRAM-based PUF generators202512,380,950Non-volatile static random access memory (NVSRAM) with multiple magnetic tunnel junction cells202512,284,804Memory devices, semiconductor devices, and methods of operations a memory device202512,260,904Memory device with additional write bit lines202512,260,654Pedestrian detection via a boundary cylinder model202512,254,923Nonvolatile SRAM202512,190,986Sense amplifier for coupling effect reduction202512,190,945SRAM power-up random number generator202512,087,345Balanced negative bitline voltage for a write assist circuit202412,022,014Physically unclonable function (PUF) generation202411,984,164Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells202411,949,799I/O circuit design for SRAM-based PUF generators202411,903,188Memory devices, semiconductor devices, and methods of operating a memory device202411,810,635Sense amplifier for coupling effect reduction202311,657,873Non-volatile static random access memory (nvSRAM) with multiple magnetic tunnel junction cells202311,626,157SRAM power-up random number generator202311,601,117Sense amplifier for coupling effect reduction202311,545,218Nonvolatile SRAM202311,532,351Memory device with additional write bit lines202211,528,151Physically unclonable function (PUF) generation202211,238,908Memory circuit and method of operating same202211,200,924Method of minimizing read-disturb-write effect of SRAM circuit and SRAM circuit thereof202111,195,567Balanced negative bitline voltage for a write assist circuit202111,189,342Memory macro and method of operating the same2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (23)· patent assignee history
2021–2025Based in TW· patent location history
2025Patents assigned to VOLVO CAR CORP (1)· patent assignee history
2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG CO LTD | 23 | 2021–2025 |
| VOLVO CAR CORP | 1 | 2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| TW | 23 | 2021–2025 |
| US | 1 | 2025 |