Inventor
LAKSHMINARAYANAN STRIRAMASSARMA
Inventor
US
Overview
Patents· 40 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Tprimary
G06TImage data processing or generation, in general29%
G06FElectric digital data processing27%
G06NComputing arrangements based on specific computational models18%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use12%
H03MCoding10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h104%
G11CStatic stores1%
PatentTitleYear
12,579,072Graphics processor register file including a low energy portion and a high capacity portion202612,554,674Multi-tile memory management202612,386,779Dynamic memory reconfiguration202512,306,771Efficient data sharing for graphics data processing operations202512,293,431Sparse optimizations for a matrix accelerator architecture202512,210,477Systems and methods for improving cache efficiency and utilization202512,204,487Graphics processor data access and sharing202512,182,062Multi-tile memory management202412,182,035Systems and methods for cache optimization202412,153,541Cache structure and utilization202412,141,890Enabling product SKUs based on chiplet configurations202412,141,094Systolic disaggregation within a matrix accelerator architecture202412,124,383Systems and methods for cache optimization202412,112,398Disaggregation of system-on-chip (SOC) architecture202412,099,461Multi-tile memory management202412,094,048Multi-tile graphics processor rendering202412,066,975Cache structure and utilization202412,056,789Disaggregation of system-on-chip (SOC) architecture202412,056,059Systems and methods for cache optimization202412,032,496Efficient data sharing for graphics data processing operations202412,013,808Multi-tile architecture for graphics operations202411,995,029Multi-tile memory management for detecting cross tile access providing multi-tile inference scaling and providing page migration202411,954,062Dynamic memory reconfiguration202411,934,342Assistance for hardware prefetch in cache access202411,908,542Energy efficient memory array with optimized burst read and write data access202411,892,950Data prefetching for graphics data processing202411,868,264Sector cache for compression202411,763,416Disaggregation of system-on-chip (SOC) architecture202311,755,501Efficient data sharing for graphics data processing operations202311,756,150Disaggregation of system-on-chip (SOC) architecture202311,676,239Sparse optimizations for a matrix accelerator architecture202311,620,256Systems and methods for improving cache efficiency and utilization202311,593,269Sector cache for compression202311,586,548Sector cache for compression202311,410,266Disaggregation of System-On-Chip (SOC) architecture202211,409,658Data prefetching for graphics data processing202211,386,521Enabling product SKUS based on chiplet configurations202211,301,384Partial write management in a multi-tiled compute engine202211,263,141Sector cache for compression202211,145,105Multi-tile graphics processor rendering2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (40)· patent assignee history
2021–2026Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 40 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 40 | 2021–2026 |