LexDanaLexDanabeta
Inventor

Soon-Moon Jung

Inventor
Gyeonggi-do, KR

Overview

66→
Patents
1998–2013
Patent span
Electricity
Primary field (CPC H)

Patents· 66 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary
H10DInorganic electric semiconductor devices31%
H10BElectronic memory devices30%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
G11CStatic stores12%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h105%
B42DBooks2%
H10NElectric solid-state devices not otherwise provided for2%
A63CSkates1%
H02JElectric power networks1%
PatentTitleYear
8,399,308'Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines'20138,343,812'Contact structures in substrate having bonded interface, semiconductor device including the same, methods of fabricating the same'20138,324,045'Method of forming semiconductor device having common node that contacts plural stacked active elements and that has resistive memory elements corresponding to the active elements'20128,258,517'Semiconductor device having driving transistors'20128,258,563'Multi-layer memory devices'20128,248,853'Methods of programming non-volatile flash memory devices by applying a higher voltage level to a selected word line than to a word line neighboring the selected word line'20128,227,306'Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof'20128,227,919'Interconnection structure and electronic device employing the same'20128,183,634'Stack-type semiconductor device'20128,168,530'Methods of forming one transistor DRAM devices'20128,084,306'Methods of forming semiconductor devices having self-aligned bodies'20118,054,688'Non-volatile memory device and erase method'20118,048,727'Methods of forming SRAM devices having buried layer patterns'20118,040,733'Non-volatile memory device and method of operating the same'20118,034,668'Method for forming semiconductor device having metallization comprising select lines, bit lines and word lines'20118,026,504'Semiconductor device and method of forming the same'20118,004,885'Three-dimensional memory device and driving method thereof'20117,982,221'Semiconductor memory device having three dimensional structure'20117,978,561'Semiconductor memory devices having vertically-stacked transistors therein'20117,960,844'3-dimensional flash memory device, method of fabrication and method of operation'20117,936,002'Multiple-layer non-volatile memory devices, memory systems employing such devices, and methods of fabrication thereof'20117,927,932'Semiconductor device having a plurality of stacked transistors and method of fabricating the same'20117,910,433'Methods of fabricating multi-layer nonvolatile memory devices'20117,825,472'Semiconductor device having a plurality of stacked transistors and method of fabricating the same'20107,795,651'One transistor DRAM device and method of forming the same'20107,719,033'Semiconductor devices having thin film transistors and methods of fabricating the same'20107,709,323'Methods of forming nand-type nonvolatile memory devices'20107,701,771'Memory device including 3-dimensionally arranged memory cell transistors and methods of operating the same'20107,683,404'Stacked memory and method for forming the same'20107,671,389'SRAM devices having buried layer patterns'20107,646,664'Semiconductor device with three-dimensional array structure'20107,626,228'NAND-type non-volatile memory devices having a stacked structure'20097,602,028'NAND flash memory devices having 3-dimensionally arranged memory cells and methods of fabricating the same'20097,601,998'Semiconductor memory device having metallization comprising select lines, bit lines and word lines'20097,592,625'Semiconductor transistor with multi-level transistor structure and method of fabricating the same'20097,589,992'Semiconductor device having three dimensional structure'20097,589,375'Non-volatile memory devices including etching protection layers and methods of forming the same'20097,586,135'Multilevel integrated circuit devices and methods of forming the same'20097,563,683'Transistor and method of fabricating the same'20097,554,140'Nand-type non-volatile memory device'20097,521,715'Node contact structures in semiconductor devices'20097,511,297'Phase change memory device and method of fabricating the same'20097,485,535'Methods of fabricating semiconductor devices with a source/drain formed on a recessed portion of an isolation layer'20097,479,673'Semiconductor integrated circuits with stacked node contact structures'20097,432,560'Body-tied-to-source MOSFETs with asymmetrical source and drain regions and methods of fabricating the same'20087,417,286'Semiconductor integrated circuit devices having single crystalline thin film transistors and methods of fabricating the same'20087,405,450'Semiconductor devices having high conductivity gate electrodes with conductive line patterns thereon'20087,387,919'Methods of fabricating a semiconductor device having a node contact structure of a CMOS inverter'20087,315,466'Semiconductor memory device and method for arranging and manufacturing the same'20087,312,144'Unitary interconnection structures integral with a dielectric layer and fabrication methods thereof'20077,312,110'Methods of fabricating semiconductor devices having thin film transistors'20077,276,421'Method of forming single crystal semiconductor thin film on insulator and semiconductor device fabricated thereby'20077,276,404'Methods of forming SRAM cells having landing pad in contact with upper and lower cell gate patterns'20077,247,528'Methods of fabricating semiconductor integrated circuits using selective epitaxial growth and partial planarization techniques'20077,193,276'Semiconductor devices with a source/drain regions formed on a recessed portion of an isolation layer'20077,170,133'Transistor and method of fabricating the same'20077,151,031'Methods of fabricating semiconductor devices having gate insulating layers with differing thicknesses'20067,141,851'Transistors having a recessed channel region'20067,135,746'SRAM cells having landing pad in contact with upper and lower cell gate patterns and methods of forming the same'20066,870,231'Layouts for CMOS SRAM cells and devices'20056,806,180'Unitary interconnection structures integral with a dielectric layer'20046,376,368'Method of forming contact structure in a semiconductor device'20026,335,279'Method of forming contact holes of semiconductor device'20026,288,926'Static semiconductor memory device and fabricating method thereof'20015,852,572'Small-sized static random access memory cell'19985,843,811'Method of fabricating a crystalline thin film on an amorphous substrate'1998

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1998–2013Patents assigned to SAMSUNG ELECTRONICS CO LTD (65)· patent assignee history
1998–2013Based in Seongnam-si, KR· patent location history
2002–2012Based in Gyeonggi-do, KR· patent location history
2004–2013Based in Yongin-si, KR· patent location history
2010–2011Based in Seoul, KR· patent location history
2011–2013Patents assigned to JUNG SOON-MOON (10)· patent assignee history
2011–2012Patents assigned to JEONG JAE-HUN (4)· patent assignee history
2011–2012Based in Seongnam, KR· patent location history
2012–2013Patents assigned to JANG JAE-HOON (4)· patent assignee history
2012–2013Patents assigned to KIM HAN-SOO (4)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
SAMSUNG ELECTRONICS CO LTD651998–2013
JUNG SOON-MOONself102011–2013
JANG JAE-HOON42012–2013
JEONG JAE-HUN42011–2012
KIM HAN-SOO42012–2013
Locations
LocationPatentsSpan
Gyeonggi-do, KR332002–2012
Seongnam-si, KR181998–2013
Yongin-si, KR72004–2013
Seongnam, KR22011–2012
Seoul, KR22010–2011