Inventor
Wayne F. Ellis
Inventor
Jericho, VT, US
Overview
Patents· 90 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G11Cprimary
G11CStatic stores39%
G06FElectric digital data processing18%
G01RMeasuring electric variables8%
H10DInorganic electric semiconductor devices6%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h105%
H10BElectronic memory devices5%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h103%
H01LSemiconductor devices2%
PatentTitleYear
11,081,1762T-1R architecture for resistive RAM202110,878,878Protocol for memory power-mode control202010,783,9641T-1R architecture for resistive random access memory202010,698,464Multi-element memory device with power control for individual elements202010,672,450Protocol for memory power-mode control202010,650,872Memory component with multiple command/address sampling modes202010,622,0622T-1R architecture for resistive ram202010,622,053Protocol for memory power-mode control202010,614,869Protocol for memory power-mode control202010,600,497Timing-drift calibration202010,431,290Protocol for memory power-mode control201910,388,3721T-1R architecture for resistive random access memory201910,262,718DRAM having a plurality of registers201910,209,922Communication via a memory interface201910,199,0982T-1R architecture for resistive RAM201910,198,314Memory device with in-system repair capability201910,170,170Memory control component with dynamic command/address signaling rate201910,037,8012T-1R architecture for resistive RAM20189,965,012Multi-element memory device with power control for individual elements20189,886,993'Protocol for memory power-mode control'20189,859,021'Timing-drift calibration'20189,824,752'1T-1R architecture for resistive random access memory'20179,818,463'Memory control component with inter-rank skew tolerance'20179,575,835'Error correction in a memory device'20179,563,597'High capacity memory systems with inter-rank skew tolerance'20179,502,096'Protocol for memory power-mode control'20169,431,131'Timing-drift calibration'20169,411,678'DRAM retention monitoring method for dynamic error correction'20169,401,225'Timing-drift calibration'20169,390,798'1T-1R architecture for resistive random access memory'20169,362,006'Timing-drift calibration'20169,256,279'Multi-element memory device with power control for individual elements'20169,129,666'Robust commands for timing calibration or recalibration'20159,098,209'Communication via a memory interface'20159,064,730'Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device'20159,037,949'Error correction in a memory device'20158,947,965'Techniques for providing a direct injection semiconductor memory device'20158,942,056'Protocol for memory power-mode control'20158,710,566'Techniques for forming a contact to a buried diffusion layer in a semiconductor memory device'20148,315,099'Techniques for providing a direct injection semiconductor memory device'20128,138,610'Multi-chip package with interconnected stacked chips'20128,099,688'Circuit design'20127,975,170'Memory refresh system and method'20117,944,047'Method and structure of expanding, upgrading, or fixing multi-chip package'20117,882,324'Method and apparatus for synchronizing memory enabled systems with master-slave architecture'20117,721,010'Method and apparatus for implementing memory enabled systems using master-slave architecture'20107,694,196'Self-diagnostic scheme for detecting errors'20107,688,665'Structure to share internally generated voltages between chips in MCP'20107,565,585'Integrated redundancy architecture and method for providing redundancy allocation to an embedded memory system'20097,539,034'Memory configured on a common substrate'20097,480,774'Method for performing a command cancel function in a DRAM'20097,466,604'SRAM voltage control for improved operational margins'20087,413,833'Single exposure of mask levels having a lines and spaces array using alternating phase-shift mask'20087,394,268'Carrier for test, burn-in, and first level packaging'20087,313,032'SRAM voltage control for improved operational margins'20077,305,515'Performance optimizing compiler for building a compiled DRAM'20077,193,262'Low-cost deep trench decoupling capacitor device and process of manufacture'20077,132,841'Carrier for test, burn-in, and first level packaging'20067,085,971'ECC based system and method for repairing failed memory elements'20066,912,665'Automatic timing analyzer'20056,826,113'Synchronous dynamic random access memory device having memory command cancel function'20046,737,907'Programmable DC voltage generator system'20046,731,179'System and method for measuring circuit performance degradation due to PFET negative bias temperature instability (NBTI)'20046,670,667'Asymmetric gates for high density DRAM'20036,646,949'Word line driver for dynamic random access memories'20036,580,650'DRAM word line voltage control to insure full cell writeback level'20036,538,932'Timing circuit and method for a compilable DRAM'20036,507,237'Low-power DC voltage generator system'20036,458,646'Asymmetric gates for high density DRAM'20026,452,855'DRAM array interchangeable between single-cell and twin-cell array operation'20026,426,904'Structures for wafer level test and burn-in'20026,373,771'Integrated fuse latch and shift register for efficient programming and fuse readout'20026,358,627'Rolling ball connector'20026,337,595'Low-power DC voltage generator system'20026,320,803'Method and apparatus for improving the testing, yield and performance of very large scale integrated circuits'20016,252,806'Multi-generator, partial array Vt tracking system to improve array retention time'20016,233,184'Structures for wafer level test and burn-in'20016,177,729'Rolling ball connector'20016,121,106'Method for forming an integrated trench capacitor'20005,875,470'Multi-port multiple-simultaneous-access DRAM chip'19995,703,823'Memory device with programmable self-refreshing and testing methods therefore'19975,559,050'P-MOSFETS with enhanced anomalous narrow channel effect'19965,463,335'Power up detection circuits'19955,446,695'Memory device with programmable self-refreshing and testing methods therefore'19955,418,738'Low voltage programmable storage element'19955,334,880'Low voltage programmable storage element'19945,265,056'Signal margin testing system for dynamic RAM'19935,157,635'Input signal redriver for semiconductor modules'19924,992,984'Memory module utilizing partially defective memory chips'19914,542,310'CMOS bootstrapped pull up circuit'1985Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1985–2012Patents assigned to IBM (42)· patent assignee history
1985–2020Based in Jericho, VT, US· patent location history
2011–2012Patents assigned to QIMONDA AG (4)· patent assignee history
2012–2015Patents assigned to MICRON TECHNOLOGY INC (4)· patent assignee history
2012–2020Based in Saratoga, CA, US· patent location history
2014–2015Based in Los Gatos, CA, US· patent location history
2015–2020Patents assigned to RAMBUS INC (29)· patent assignee history
2015–2019Based in Campbell, CA, US· patent location history
2017–2021Based in Jericho Center, VT, US· patent location history
2018–2021Patents assigned to HEFEI RELIANCE MEMORY LTD (6)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 42 | 1985–2012 |
| RAMBUS INC | 29 | 2015–2020 |
| HEFEI RELIANCE MEMORY LTD | 6 | 2018–2021 |
| MICRON TECHNOLOGY INC | 4 | 2012–2015 |
| QIMONDA AG | 4 | 2011–2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Jericho, VT, US | 52 | 1985–2020 |
| Jericho Center, VT, US | 15 | 2017–2021 |
| Campbell, California, US | 11 | 2015–2019 |
| Saratoga, California, US | 10 | 2012–2020 |
| Los Gatos, California, US | 2 | 2014–2015 |