Inventor
Dennis A. Schmidt
Inventor
South Burlington, VT, US
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1028%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
B23KSoldering or unsoldering10%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices10%
H10DInorganic electric semiconductor devices10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
G01RMeasuring electric variables5%
H05KPrinted circuits5%
B24BMachines, devices, or processes for grinding or polishing3%
B65BMachines, apparatus or devices for, or methods of, packaging articles or materials3%
PatentTitleYear
10,351,280Method for handling containers, in particular cardboard boxes, for groups of objects, in particular packages20196,943,452'Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality'20056,388,198'Coaxial wiring within SOI semiconductor, PCB to system for high speed operation and signal quality'20026,333,546'Micro fusible link for semiconductor devices and method of manufacture'20016,294,453'Micro fusible link for semiconductor devices and method of manufacture'20016,246,583'Method and apparatus for removing heat from a semiconductor device'20016,242,778'Cooling method for silicon on insulator devices'20016,190,836'Methods for repair of photomasks'20016,165,649'Methods for repair of photomasks'20006,156,461'Method for repair of photomasks'20006,090,507'Methods for repair of photomasks'20005,925,924'Methods for precise definition of integrated circuit chip edges'19995,872,025'Method for stacked three dimensional device manufacture'19995,691,248'Methods for precise definition of integrated circuit chip edges'19975,679,609'Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses'19975,661,330'Fabrication, testing and repair of multichip semiconductor structures having connect assemblies with fuses'19975,658,185'Chemical-mechanical polishing apparatus with slurry removal system and method'19975,651,857'Sidewall spacer using an overhang'19974,386,729'Self-locking design for octagonal container'1983Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1983Patents assigned to INT PAPER CO (1)· patent assignee history
1983Based in Fond du Lac, WI, US· patent location history
1997–2005Patents assigned to IBM (17)· patent assignee history
1997–2005Based in South Burlington, VT, US· patent location history
2019Patents assigned to FOCKE & CO (1)· patent assignee history
2019Based in Westoverledingen, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 1997–2005 |
| FOCKE & CO | 1 | 2019 |
| INT PAPER CO | 1 | 1983 |
Locations
| Location | Patents | Span |
|---|---|---|
| South Burlington, VT, US | 17 | 1997–2005 |
| Westoverledingen, DE | 1 | 2019 |
| Fond du Lac, WI, US | 1 | 1983 |