LexDanaLexDanabeta
Inventor

Om P. Agrawal

Inventor
Los Altos, CA, US

Overview

143→
Patents
1988–2017
Patent span
Electricity
Primary field (CPC H)

Patents· 143 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary
H03KPulse technique73%
G06FElectric digital data processing12%
G05BControl or regulating systems in general5%
H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses3%
G11CStatic stores2%
G06JHybrid computing arrangements1%
G01RMeasuring electric variables1%
H03MCoding1%
H04LTransmission of digital information, e.g. telegraphic communication1%
H04WWireless communication networks1%
PatentTitleYear
9,648,474'Efficiently transmitting bulk data over a mobile network'20178,122,277'Clock distribution chip'20128,112,656'Clock distribution chip'20127,957,208'Flexible memory architectures for programmable logic devices'20117,787,326'Programmable logic device with a multi-data rate SDRAM interface'20107,702,977'Programmable logic devices with custom identification systems and methods'20107,696,784'Programmable logic device with multiple slice types'20107,675,321'Dual-slice architectures for programmable logic devices'20107,657,773'Clock distribution chip for generating both zero-delay and non-zero-delay clock signals'20107,605,606'Area efficient routing architectures for programmable logic devices'20097,592,834'Logic block control architectures for programmable logic devices'20097,573,291'Programmable logic device with enhanced logic block architecture'20097,554,358'Programmable logic devices with user non-volatile memory'20097,546,498'Programmable logic devices with custom identification systems and methods'20097,495,970'Flexible memory architectures for programmable logic devices'20097,459,935'Programmable logic devices with distributed memory'20087,459,931'Programmable logic devices with transparent field reconfiguration'20087,427,874'Interface block architectures'20087,397,276'Logic block control architectures for programmable logic devices'20087,385,417'Dual slice architectures for programmable logic devices'20087,378,873'Programmable logic device providing a serial peripheral interface'20087,378,872'Programmable logic device architecture with multiple slice types'20087,355,441'Programmable logic devices with distributed memory and non-volatile memory'20087,342,838'Programmable logic device with a double data rate SDRAM interface'20087,327,159'Interface block architectures'20087,327,160'SERDES with programmable I/O architecture'20087,295,035'Programmable logic device with enhanced logic block architecture'20077,256,613'Programmable interconnect architecture for programmable logic devices'20077,215,139'Upgradeable and reconfigurable programmable logic device'20077,208,975'SERDES with programmable I/O architecture'2007RE039510'FPGA integrated circuit having embedded sram memory blocks with registered address and data input sections'20077,154,298'Block-oriented architecture for a programmable interconnect circuit'20067,098,685'Scalable serializer-deserializer architecture and programmable interface'20067,088,134'Programmable logic device with flexible memory allocation and routing'20067,081,771'Upgradeable and reconfigurable programmable logic device'20067,061,269'I/O buffer architecture for programmable devices'20067,034,599'Clock generator with skew control'20067,028,281'FPGA with register-intensive architecture'20067,019,577'Clock generator'20067,000,212'Hierarchical general interconnect architecture for high density FPGA\'S'20066,922,078'Programmable logic device with enhanced wide and deep logic capability'20056,919,736'Field programmable gate array having embedded memory with configurable depth and width'20056,885,227'Clock generator with skew control'20056,879,182'CPLD with multi-function blocks and distributed memory'20056,864,713'Multi-stage interconnect architecture for complex programmable logic devices'20056,861,871'Cascaded logic block architecture for complex programmable logic devices'20056,861,868'High speed interface for a programmable interconnect circuit'20056,838,904'Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation'20056,828,823'Non-volatile and reconfigurable programmable logic devices'20046,753,696'Programmable optimized-distribution logic allocator for a high-density complex PLD'20046,703,860'I/O block for a programmable interconnect circuit'20046,661,254'Programmable interconnect circuit with a phase-locked loop'20036,653,860'Enhanced macrocell module having expandable product term sharing capability for use in high density CPLD architectures'20036,653,861'Multi-level routing structure for a programmable interconnect circuit'20036,650,142'Enhanced CPLD macrocell module having selectable bypass of steering-based resource allocation and methods of use'20036,650,141'High speed interface for a programmable interconnect circuit'20036,621,298'Variable grain architecture for FPGA integrated circuits'20036,590,415'Methods for configuring FPGA\'s having variable grain components for providing time-shared access to interconnect resources'20036,567,969'Configurable logic array including lookup table means for generating functions of different numbers of input terms'20036,531,890'Programmable optimized-distribution logic allocator for a high-density complex PLD'20036,526,558'Methods for configuring FPGA\'s having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources'20036,380,759'Variable grain architecture for FPGA integrated circuits'20026,348,813'Scalable architecture for high density CPLD\'s having two-level hierarchy of routing resources'20026,292,930'Methods for configuring FPGA\'s having variable grain blocks and shared logic for providing time-shared access to interconnect resources'20016,275,064'Symmetrical, extended and fast direct connections between variable grain blocks in FPGA integrated circuits'20016,249,144'Methods for configuring FPGA\'s having variable grain components for providing time-shared access to interconnect resources'20016,216,257'FPGA device and method that includes a variable grain function architecture for implementing configuration logic blocks and a complimentary variable length interconnect architecture for providing configurable routing between configuration logic blocks'20016,211,695'FPGA integrated circuit having embedded SRAM memory blocks with registered address and data input sections'20016,204,686'Methods for configuring FPGA\'s having variable grain blocks and shared logic for providing symmetric routing of result output to differently-directed and tristateable interconnect resources'20016,191,612'Enhanced I/O control flexibility for generating control signals'20016,184,713'Scalable architecture for high density CPLDS having two-level hierarchy of routing resources'20016,181,163'FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals'20016,163,168'Efficient interconnect network for use in FPGA device having variable grain architecture'20006,154,051'Tileable and compact layout for super variable grain blocks within FPGA device'20006,150,841'Enhanced macrocell module for high density CPLD architectures'20006,150,842'Variable grain architecture for FPGA integrated circuits'20006,130,551'Synthesis-friendly FPGA architecture with variable length and variable timing interconnect'20006,128,770'Configurable logic array including IOB to longlines interconnect means for providing selectable access to plural longlines from each IOB (input/output block)'20006,127,843'Dual port SRAM memory for run time use in FPGA integrated circuits'20006,124,730'Methods for configuring FPGA\'s having variable grain components for providing time-shared access to interconnect resources'20006,107,823'Programmable control multiplexing for input/output blocks (IOBs) in FPGA integrated circuits'20006,102,963'Electrically erasable and reprogrammable, nonvolatile integrated storage device with in-system programming and verification (ISPAV) capabilities for supporting in-system reconfiguring of PLD\'s'20006,100,715'Methods for configuring FPGA\'s having variable grain blocks and logic for providing time-shared access to interconnect resources'20006,097,212'Variable grain architecture for FPGA integrated circuits'20006,097,664'Multi-port SRAM cell array having plural write paths including for writing through addressable port and through serial boundary scan'20006,081,473'FPGA integrated circuit having embedded sram memory blocks each with statically and dynamically controllable read mode'20006,034,544'Programmable input/output block (IOB) in FPGA integrated circuits'20006,028,446'Flexible synchronous and asynchronous circuits for a very high density programmable logic device'20005,990,702'Flexible direct connections between input/output blocks (IOBs) and variable grain blocks (VGBs) in FPGA integrated circuits'19995,982,193'Input/output block (IOB) connections to MaxL lines, nor lines and dendrites in FPGA integrated circuits'19995,869,981'High density programmable logic device'19995,818,254'Multi-tiered hierarchical high speed switch matrix structure for very high-density complex programmable logic devices'19985,811,986'Flexible synchronous/asynchronous cell structure for a high density programmable logic device'19985,789,939'Method for providing a plurality of hierarchical signal paths in a very high-density programmable logic device'19985,781,030'Programmable uniform symmetrical distribution logic allocator for a high-density complex PLD'19985,764,078'Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix'19985,740,069'Logic device (PLD) having direct connections between configurable logic blocks (CLBs) and configurable input/output blocks (IOBs)'19985,644,496'Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses'19975,621,650'Programmable logic device with internal time-constant multiplexing of signals from external interconnect buses'19975,617,042'Multiple array programmable logic device with a plurality of programmable switch matrices'19975,612,631'An I/O macrocell for a programmable logic device'19975,598,346'Array of configurable logic blocks including network means for broadcasting clock signals to different pluralities of logic blocks'19975,594,365'Flexible block clock generation circuit for providing clock signals to clocked elements in a multiple array high density programmable logic device'19975,587,921'Array of configurable logic blocks each including a look up table having inputs coupled to a first multiplexer and having outputs coupled to a second multiplexer'19965,586,044'Array of configurable logic blocks including cascadable lookup tables'19965,521,529'Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation'19965,489,857'Flexible synchronous/asynchronous cell structure for a high density programmable logic device'19965,490,074'Constant delay interconnect for coupling configurable logic blocks'19965,485,104'Logic allocator for a programmable logic device'19965,469,368'Array of configurable logic blocks each including a first lookup table output coupled to selectively replace an output of second lookup with an alternate function output'19955,457,409'Architecture of a multiple array high density programmable logic device with a plurality of programmable switch matrices'19955,436,514'High speed centralized switch matrix for a programmable logic device'19955,426,335'Pinout architecture for a family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix'19955,422,823'Programmable gate array device having cascaded means for function definition'19955,359,536'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block'19945,349,544'Programmable system synchronizer'19945,349,670'Integrated circuit programmable sequencing element apparatus'19945,329,460'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block'19945,261,116'Programmable, expandable controller with flexible I/O'19935,260,881'Programmable gate array with improved configurable logic block'19935,255,203'Interconnect structure for programmable logic device'19935,247,195'PLDs with high drive capability'19935,239,213'Precision timing control programmable logic device'19935,233,539'Programmable gate array with improved interconnect structure, input/output structure and configurable logic block'19935,231,588'Programmable gate array with logic cells having symmetrical input/output structures'19935,225,719'Family of multiple segmented programmable logic blocks interconnected by a high speed centralized switch matrix'19935,212,652'Programmable gate array with improved interconnect structure'19935,191,242'Programmable logic device incorporating digital-to-analog converter'19935,185,706'Programmable gate array with logic cells having configurable output enable'19935,179,716'Programmable expandable controller with flexible I/O'19935,168,177'Programmable logic device with observability and preloadability for buried state registers'19925,153,462'Programmable logic device incorporating voltage comparator'19925,151,623'Programmable logic device with multiple, flexible asynchronous programmable logic blocks interconnected by a high speed switch matrix'19925,042,004'Programmable logic device with subroutine stack and random access memory'19915,027,315'Programmable logic array using internally generated dynamic logic signals as selection signals for controlling its functions'19915,015,884'Multiple array high performance programmable logic device family'19914,963,768'Flexible, programmable cell array interconnected by a programmable switch matrix'19904,933,897'Method for designing a control sequencer'19904,931,671'Multiple array customizable logic device'19904,876,640'Logic controller having programmable logic \"and\" array using a programmable gray-code counter'19894,779,229'Prom with programmable output structures'19884,771,285'Programmable logic cell with flexible clocking and flexible feedback'19884,742,252'Multiple array customizable logic device'1988

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1988–2000Patents assigned to ADVANCED MICRO DEVICES INC (54)· patent assignee history
1988–2003Based in San Jose, CA, US· patent location history
1995–2012Based in Los Altos, CA, US· patent location history
1999–2002Patents assigned to VANTIS CORP (22)· patent assignee history
2000–2012Patents assigned to LATTICE SEMICONDUCTOR CORP (66)· patent assignee history
2012Patents assigned to AGRAWAL OM (2)· patent assignee history
2012Patents assigned to CHANDRA SHYAM (2)· patent assignee history
2017Based in Saskatoon, CA· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
LATTICE SEMICONDUCTOR CORP662000–2012
ADVANCED MICRO DEVICES INC541988–2000
VANTIS CORP221999–2002
AGRAWAL OMself22012
CHANDRA SHYAM22012
Locations
LocationPatentsSpan
Los Altos, California, US991995–2012
San Jose, California, US431988–2003
Saskatoon, CA12017