Inventor
Matthew M. Ziegler
Inventor
Sleepy Hollow, NY, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing70%
G06NComputing arrangements based on specific computational models15%
H02MApparatus for conversion between ac and ac, between ac and dc, or between dc and dc, and for use with mains or similar power supply systems7%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications7%
PatentTitleYear
10,789,400Scheduling simultaneous optimization of multiple very-large-scale-integration designs202010,296,691Optimizing the layout of circuits based on multiple design constraints201910,263,519Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time201910,083,268Scheduling simultaneous optimization of multiple very-large-scale-integration designs201810,002,221Enhanced parameter tuning for very-large-scale integration synthesis20189,934,344Enhanced parameter tuning for very-large-scale integration synthesis20189,910,949'Synthesis tuning system for VLSI design optimization'20189,703,920'Intra-run design decision process for circuit synthesis'20179,690,900'Intra-run design decision process for circuit synthesis'20179,660,530'Resonant virtual supply booster for synchronous digital circuits having a predictable evaluate time'20179,619,602'Enhanced parameter tuning for very-large-scale integration synthesis'20179,600,623'Scheduling simultaneous optimization of multiple very-large-scale-integration designs'20179,582,627'Enhanced parameter tuning for very-large-scale integration synthesis'20179,529,951'Synthesis tuning system for VLSI design optimization'20168,954,914'Graphical method and product to assign physical attributes to entities in a high level descriptive language used for VLSI chip design'20158,839,162'Specifying circuit level connectivity during circuit design synthesis'20148,756,541'Relative ordering circuit synthesis'20148,566,761'Network flow based datapath bit slicing'20138,516,412'Soft hierarchy-based physical synthesis for large-scale, high-performance circuits'20138,495,552'Structured latch and local-clock-buffer planning'20138,271,920'Converged large block and structured synthesis for high performance microprocessor designs'2012Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2012–2020Patents assigned to IBM (21)· patent assignee history
2012–2014Patents assigned to PURI RUCHIR (6)· patent assignee history
2012–2014Patents assigned to CHO MINSIK (5)· patent assignee history
2012–2014Patents assigned to REN HAOXING (5)· patent assignee history
2012–2014Patents assigned to XIANG HUA (5)· patent assignee history
2012–2020Based in Sleepy Hollow, NY, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 21 | 2012–2020 |
| PURI RUCHIR | 6 | 2012–2014 |
| CHO MINSIK | 5 | 2012–2014 |
| REN HAOXING | 5 | 2012–2014 |
| XIANG HUA | 5 | 2012–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Sleepy Hollow, New York, US | 21 | 2012–2020 |