Inventor
Dhawal BAVISHI
Inventor
US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing79%
G11CStatic stores7%
H04LTransmission of digital information, e.g. telegraphic communication7%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
PatentTitleYear
12,346,612Memory sub-system command fencing202512,236,131Controller command scheduling in a memory system to increase command bus utilization202512,007,917Priority scheduling in queues to access cache data in a memory sub-system202412,007,898Utilizing a designated memory address to pre-fetch for memory sub-system with cache202411,983,435Optimize information requests to a memory system202411,941,291Memory sub-system command fencing202411,914,520Separate read-only cache and write-read cache in a memory sub-system202411,847,058Using a second content-addressable memory to manage memory burst accesses in memory sub-systems202311,809,710Outstanding transaction monitoring for memory sub-systems202311,748,273Secure data communication with memory sub-system202311,740,833Throttle response signals from a memory system202311,741,008Disassociating memory units with a host system202311,698,756Cache-based memory read commands202311,675,705Eviction of a cache line based on a modification of a sector of the cache line202311,669,265Memory sub-system-bounded memory function202311,656,995Dynamic access granularity in a cache media202311,650,755Proactive return of write credits in a memory system202311,636,047Hash operations in memory for data sharing202311,609,855Bit masking valid sectors for write-back coalescing202311,604,749Direct memory access (DMA) commands for noncontiguous source and destination memory addresses202311,573,743Pointer dereferencing within memory sub-system202311,573,700Buffer management in memory systems for read and write requests202311,461,256Quality of service levels for a direct memory access engine in a memory sub-system202211,449,419Disassociating memory units with a host system202211,442,867Using a second content-addressable memory to manage memory burst accesses in memory sub-systems202211,409,436Buffer management in memory systems for read and write requests202211,288,199Separate read-only cache and write-read cache in a memory sub-system202211,262,946Cache-based memory read commands202211,249,924Secure data communication with memory sub-system202211,210,225Pre-fetch for memory sub-system with cache where the pre-fetch does not send data and response signal to host202111,194,518Pointer dereferencing within memory sub-system202111,163,486Memory sub-system-bounded memory function202111,157,412Read commands based on row status prediction2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to MICRON TECHNOLOGY INC (33)· patent assignee history
2021–2025Based in US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MICRON TECHNOLOGY INC | 33 | 2021–2025 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 33 | 2021–2025 |