Inventor
Karthik Jambunathan
Inventor
Hillsboro, OR, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10DInorganic electric semiconductor devices33%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%
B82YSpecific uses or applications of nanostructures7%
PatentTitleYear
11,121,030Transistors employing carbon-based etch stop layer for preserving source/drain material during contact trench etch202111,101,356Doped insulator cap to reduce source/drain diffusion for germanium NMOS transistors202111,101,350Integrated circuit with germanium-rich channel transistors including one or more dopant diffusion barrier elements202111,101,268Transistors employing non-selective deposition of source/drain material202111,081,570Transistors with lattice matched gate structure202111,069,795Transistors with channel and sub-channel regions with distinct compositions and dimensions202111,056,592Silicon substrate modification to enable formation of thin, relaxed, germanium-based layer202111,024,737Etching fin core to provide fin doubling202111,011,620Techniques for increasing channel region tensile strain in n-MOS devices202111,004,978Methods of forming doped source/drain contacts and structures formed thereby202111,004,954Epitaxial buffer to reduce sub-channel leakage in MOS transistors202110,944,006Geometry tuning of fin based transistor202110,892,337Backside source/drain replacement for semiconductor devices with metallization on both sides202110,879,241Techniques for controlling transistor sub-fin leakage202010,749,032Techniques for forming transistors including group III-V material nanowires using sacrificial group IV material layers202010,734,412Backside contact resistance reduction for semiconductor devices with metallization on both sides202010,692,973Germanium-rich channel transistors including one or more dopant diffusion barrier elements202010,672,868Methods of forming self aligned spacers for nanowire device structures202010,573,750Methods of forming doped source/drain contacts and structures formed thereby202010,559,689Crystallized silicon carbon replacement material for NMOS source/drain regions202010,516,021Reduced leakage transistors with germanium-rich channel regions201910,510,848Sub-fin sidewall passivation in replacement channel FinFETS201910,483,353Transistor including tensile-strained germanium channel201910,418,464Techniques for forming transistors on the same die with varied channel materials201910,403,752Prevention of subchannel leakage current in a semiconductor device with a fin structure201910,373,977Transistor fin formation via cladding on sacrificial core20199,997,414Ge/SiGe-channel and III-V-channel transistors on the same die2018Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2018–2021Patents assigned to INTEL CORP (27)· patent assignee history
2018–2021Based in Hillsboro, OR, US· patent location history
2020–2021Based in Portland, OR, US· patent location history
2021Based in Kirkland, WA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 27 | 2018–2021 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hillsboro, OR, US | 21 | 2018–2021 |
| Portland, OR, US | 5 | 2020–2021 |
| Kirkland, Washington, US | 1 | 2021 |