Inventor

Mayank Sharma

Inventor
White Plains, NY, US

Overview

23→
Patents
2011–2020
Patent span
Physics
Primary field (CPC G)

Patents· 23 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing32%
G11CStatic stores30%
G06NComputing arrangements based on specific computational models5%
H03MCoding5%
H04LTransmission of digital information, e.g. telegraphic communication5%
B60LPropulsion of electrically-propelled vehicles3%
G01CMeasuring distances, levels or bearings3%
G05BControl or regulating systems in general3%
G06QInformation and communication technology [ict] specially adapted for administrative, commercial, financial, managerial or supervisory purposes3%
G08GTraffic control systems3%
PatentTitleYear
10,824,543System and method for automated software test case designing based on machine learning (ML)202010,572,374System and method for automated software testing based on machine learning (ML)202010,552,383Method and system for data conversion and data model optimization202010,545,027Method and system for preventing traffic congestion of vehicles202010,423,586Method and system for synchronization of relational database management system to non-structured query language database201910,326,670System and method for enterprise data distribution20199,785,739'System and method for fluid parameterized cell evaluation'20179,260,031'Distributed charging of electrical assets'20169,092,586'Version management mechanism for fluid guard ring PCells'20158,897,062'Memory programming for a phase change memory cell'20148,868,978'Reclaiming discarded solid state devices'20148,553,474'Increased capacity heterogeneous storage elements'20138,488,397'Increased capacity heterogeneous storage elements'20138,472,224'Adjustable write bins for multi-level analog memories'20138,463,985'Constrained coding to reduce floating gate coupling in non-volatile memories'20138,464,137'Probabilistic multi-tier error correction in not-and (NAND) flash memory'20138,352,839'Encoding data into constrained memory'20138,331,168'Increased capacity heterogeneous storage elements'20128,230,276'Writing to memory using adaptive write techniques'20128,176,235'Non-volatile memories with enhanced write performance and endurance'20128,166,368'Writing a special symbol to a memory to indicate the absence of a data signal'20128,125,809'Adjustable write bins for multi-level analog memories'20128,023,345'Iteratively writing contents to memory locations using a statistical model'2011

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2011–2016Patents assigned to IBM (15)· patent assignee history
2011–2016Based in White Plains, NY, US· patent location history
2012–2014Patents assigned to SHARMA MAYANK (13)· patent assignee history
2012–2014Patents assigned to LASTRAS-MONTANO LUIS A (12)· patent assignee history
2012–2014Patents assigned to FRANCESCHINI MICHELE M (9)· patent assignee history
2012–2014Patents assigned to JAGMOHAN ASHISH (8)· patent assignee history
2012–2013Based in Yorktown Heights, NY, US· patent location history
2017Based in Noida, IN· patent location history
2019–2020Based in Bangalore, IN· patent location history
2020Based in Dublin, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
IBM152011–2016
SHARMA MAYANKself132012–2014
LASTRAS-MONTANO LUIS A122012–2014
FRANCESCHINI MICHELE M92012–2014
JAGMOHAN ASHISH82012–2014
Locations
LocationPatentsSpan
White Plains, New York, US92011–2016
Yorktown Heights, New York, US62012–2013
Bangalore, IN42019–2020
Dublin, California, US22020
Noida, IN12017