Inventor

ANAND S. MURTHY

Inventor

US

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 94 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices33%

H01LSemiconductor devices27%

B82YSpecific uses or applications of nanostructures16%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1012%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%

H10BElectronic memory devices2%

G02BOptical elements, systems or apparatus0%

G11CStatic stores0%

H03KPulse technique0%

PatentTitleYear

12,598,777Low temperature, high germanium, high boron SiGe:B pEPI with titanium silicide contacts for ultra-low PMOS contact resistivity and thermal stability2026 12,593,486Dual contact process with selective deposition2026 12,588,485Integrated circuit structures having airgaps for backside signal routing or power delivery2026 12,588,189Memory devices with vertical transistors2026 12,575,170Low temperature, high germanium, high boron SiGe:B pEPI with a silicon rich capping layer for ultra-low PMOS contact resistivity and thermal stability2026 12,575,151Gate-all-around integrated circuit structures having doped subfin2026 12,575,401Integrated circuit devices with angled transistors and angled routing tracks2026 12,563,724Two transistor memory cells with source-drain coupling in one transistor2026 12,550,401Doped STI to reduce source/drain diffusion for germanium NMOS transistors2026 12,527,078Gate-all-around integrated circuit structures having epitaxial source or drain region lateral isolation2026 12,525,295Two transistor memory cells with angled transistors2026 12,527,026Field-effect transistor with hybrid switching mechanism2026 12,520,573SiGe:GAB source or drain structures with low resistivity2026 12,520,482Memory arrays with backside components and angled transistors2026 12,506,127Package architecture of photonic system with vertically stacked dies having planarized edges2025 12,471,362Integrated circuit structures having ultra-high conductivity global routing2025 12,471,334Integrated circuit devices with angled transistors formed based on angled wafers2025 12,439,640Reduced contact resistivity with PMOS germanium and silicon doped with boron gate all around transistors2025 12,432,964Co-integrated gallium nitride (GaN) and complementary metal oxide semiconductor (CMOS) integrated circuit technology2025 12,426,342Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability2025 12,419,091Source electrode and drain electrode protection for nanowire transistors2025 12,402,387Integrated circuit structures including a titanium silicide material2025 12,363,967Integration methods to fabricate internal spacers for nanowire devices2025 12,349,420Device, method and system to provide a stressed channel of a transistor2025 12,342,574Contact resistance reduction in transistor devices with metallization on both sides2025 12,328,927Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures2025 12,328,920Nanoribbon sub-fin isolation by backside Si substrate removal etch selective to source and drain epitaxy2025 12,294,027Semiconductor device having doped epitaxial region and its methods of fabrication2025 12,288,808High aspect ratio source or drain structures with abrupt dopant profile2025 12,288,803Transistor with isolation below source and drain2025 12,237,420Fin smoothing and integrated circuit structures resulting therefrom2025 12,170,319Dual contact process with stacked metal layers2024 12,166,124Gate-all-around integrated circuit structures having germanium-doped nanoribbon channel structures2024 12,148,751Use of a placeholder for backside contact formation for transistor arrangements2024 12,119,387Low resistance approaches for fabricating contacts and the resulting structures2024 12,107,085Interconnect techniques for electrically connecting source/drain regions of stacked transistors2024 12,046,517Self-aligned 3-D epitaxial structures for MOS device fabrication2024 12,046,600Techniques for achieving multiple transistor fin dimensions on a single die2024 12,046,654Integrated circuit structures including a titanium silicide material2024 12,027,417Source or drain structures with high germanium concentration capping layer2024 12,021,081Techniques for achieving multiple transistor fin dimensions on a single die2024 12,021,149Fin smoothing and integrated circuit structures resulting therefrom2024 11,996,447Field effect transistors with gate electrode self-aligned to semiconductor fin2024 11,942,526Integrated circuit contact structures2024 11,923,410Transistor with isolation below source and drain2024 11,908,934Semiconductor device having doped epitaxial region and its methods of fabrication2024 11,869,939Integration methods to fabricate internal spacers for nanowire devices2024 11,804,523High aspect ratio source or drain structures with abrupt dopant profile2023 11,784,239Subfin leakage suppression using fixed charge2023 11,764,275Indium-containing fin of a transistor device with an indium-rich core2023 11,757,037Epitaxial oxide plug for strained transistors2023 11,757,004Transistors including source/drain employing double-charge dopants2023 11,742,346Interconnect techniques for electrically connecting source/drain regions of stacked transistors2023 11,735,670Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium NMOS transistors2023 11,699,756Source/drain diffusion barrier for germanium nMOS transistors2023 11,682,731Fin smoothing and integrated circuit structures resulting therefrom2023 11,676,965Strained tunable nanowire structures and process2023 11,670,682FINFET transistor having a doped sub fin structure to reduce channel to substrate leakage2023 11,631,737Ingaas epi structure and wet etch process for enabling III-v GAA in art trench2023 11,588,017Nanowire for transistor integration2023 11,581,406Method of fabricating CMOS FinFETs by selectively etching a strained SiGe layer2023 11,575,005Asymmetrical semiconductor nanowire field-effect transistor2023 11,557,658Transistors with high density channel semiconductor over dielectric material2023 11,557,676Device, method and system to provide a stressed channel of a transistor2023 11,538,905Nanowire transistors employing carbon-based layers2022 11,508,813Column IV transistors for PMOS integration2022 11,482,457Substrate defect blocking layers for strained channel semiconductor devices2022 11,476,344Contact resistance reduction employing germanium overlayer pre-contact metalization2022 11,456,372Multi-height finfet device by selective oxidation2022 11,450,738Source/drain regions in integrated circuit structures2022 11,444,159Field effect transistors with wide bandgap materials2022 11,444,166Backside source/drain replacement for semiconductor devices with metallization on both sides2022 11,430,787Forming crystalline source/drain contacts on semiconductor devices2022 11,430,868Buried etch-stop layer to help control transistor source/drain depth2022 11,417,655High-mobility semiconductor source/drain spacer2022 11,411,096Source electrode and drain electrode protection for nanowire transistors2022 11,404,575Diverse transistor channel materials enabled by thin, inverse-graded, germanium-based layer2022 11,387,320Transistors with high concentration of germanium2022 11,355,621Non-planar semiconductor device including a replacement channel structure2022 11,335,600Integration method for finfet with tightly controlled multiple fin heights2022 11,302,777Integration methods to fabricate internal spacers for nanowire devices2022 11,296,079PMOS and NMOS contacts in common trench2022 11,276,755Field effect transistors with gate electrode self-aligned to semiconductor fin2022 11,251,302Epitaxial oxide plug for strained transistors2022 11,251,281Contact resistance reduction employing germanium overlayer pre-contact metalization2022 11,232,948Layered substrate for microelectronic devices2022 11,233,148Reducing band-to-band tunneling in semiconductor devices2022 11,222,977Source/drain diffusion barrier for germanium NMOS transistors2022 11,205,707Optimizing gate profile for performance and gate fill2021 11,195,919Method of fabricating a semiconductor device with strained SiGe fins and a Si cladding layer2021 11,189,730Non-selective epitaxial source/drain deposition to reduce dopant diffusion for germanium nMOS transistors2021 11,177,255Transistor structures having multiple threshold voltage channel materials2021 11,164,747Group III-V semiconductor devices having asymmetric source and drain structures2021 11,152,361Techniques for achieving multiple transistor fin dimensions on a single die2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to INTEL CORP (88)· patent assignee history

2021–2026Based in US· patent location history

2022–2023Patents assigned to DAEDALUS PRIME LLC (3)· patent assignee history

2022–2025Patents assigned to SONY GROUP CORP (3)· patent assignee history

2023–2024Patents assigned to TAHOE RES LTD (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	88	2021–2026
DAEDALUS PRIME LLC	3	2022–2023
SONY GROUP CORP	3	2022–2025
TAHOE RES LTD	2	2023–2024

Locations

Location	Patents	Span
US	94	2021–2026