Inventor
BOK ENG CHEAH
Inventor
MY
Overview
Patents· 63 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1035%
H01LSemiconductor devices35%
H05KPrinted circuits13%
H10DInorganic electric semiconductor devices6%
Y02PClimate change mitigation technologies in the production or processing of goods3%
H01GCapacitors2%
H01RElectrically-conductive connections2%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h102%
H01PWaveguides1%
E05DHinges or suspension devices for doors, windows or wings1%
PatentTitleYear
12,599,013Semiconductor packages for stacked memory-on-package (SMOP) and methods of manufacturing the same202612,512,414Vertical interconnect design for improved electrical performance202512,500,175Integrated bridge frame for package substrate202512,412,784Recessed vertical interconnects for device miniaturization202512,328,816Asymmetrical laminated circuit boards for improved electrical performance202512,288,740Semiconductor package with hybrid mold layers202512,256,487Hybrid boards with embedded planes202512,218,064Molded silicon interconnects in bridges for integrated-circuit packages202512,191,281Multi-chip package with recessed memory202512,183,722Molded interconnects in bridges for integrated-circuit packages202412,142,570Composite bridge die-to-die interconnects for integrated-circuit packages202412,112,997Micro through-silicon via for transistor density scaling202412,080,628Micro through-silicon via for transistor density scaling202412,033,953Electronic device and crosstalk mitigating substrate202412,002,747Integrated bridge for die-to-die interconnects202411,955,431Interposer structures and methods for 2.5D and 3D packaging202411,942,412Interposer with flexible portion202411,887,940Integrated circuit packages with conductive element having cavities housing electrically connected embedded components202411,887,917Encapsulated vertical interconnects for high-speed applications and methods of assembling same202411,837,458Substrate with gradiated dielectric for reducing impedance mismatch202311,798,894Devices and methods for signal integrity protection technique202311,758,662Three dimensional foldable substrate with vertical side interface202311,676,910Embedded reference layers for semiconductor package substrates202311,652,026Micro through-silicon via for transistor density scaling202311,639,623Micro-hinge for an electronic device202311,574,877Semiconductor miniaturization through component placement on stepped stiffener202311,562,963Stacked semiconductor package and method of forming the same202311,562,954Frame-array interconnects for integrated-circuit packages202311,557,5523D trench reference planes for integrated-circuit die packages202311,545,434Vertical die-to-die interconnects bridge202311,540,395Stacked-component placement in multiple-damascene printed wiring boards for semiconductor package substrates202211,527,467Multi-chip package with extended frame202211,527,481Stacked semiconductor package with flyover bridge202211,527,485Electrical shield for stacked heterogeneous device integration202211,527,463Hybrid ball grid array package for high speed interconnects202211,527,479Stepped interposer for stacked chip package202211,521,932Composite bridge die-to-die interconnects for integrated-circuit packages202211,508,650Interposer for hybrid interconnect geometry202211,508,660Molded power delivery interconnect module for improved Imax and power integrity202211,482,481Semiconductor device and system202211,476,198Multi-level components for integrated-circuit packages202211,462,468Semiconductor package, semiconductor system, and method of forming semiconductor package202211,462,488Substrate cores for warpage control202211,456,516Low loss high-speed interconnects202211,430,764Overhang bridge interconnect202211,411,290Hybrid transmission line202211,398,415Stacked through-silicon vias for multi-device packages202211,393,758Power delivery for embedded interconnect bridge devices and methods202211,393,741Micro through-silicon via for transistor density scaling202211,375,617Three dimensional foldable substrate with vertical side interface202211,367,673Semiconductor package with hybrid through-silicon-vias202211,363,717Inductor array and support202211,355,458Interconnect core202211,342,289Vertical power plane module for semiconductor packages202211,289,427Multi-faceted integrated-circuit dice and packages202211,282,780Integrated bridge for die-to-die interconnects202211,284,518Semiconductor package with co-axial ball-grid-array202211,227,841Stiffener build-up layer package202211,205,622Stiffener shield for device integration202111,195,801Embedded reference layers for semiconductor package substrates202111,177,226Flexible shield for semiconductor devices202111,164,827Substrate with gradiated dielectric for reducing impedance mismatch202111,153,968Device, system and method to promote the integrity of signal communications2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (63)· patent assignee history
2021–2026Based in MY· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 63 | 2021–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| MY | 63 | 2021–2026 |