Inventor
Michael D. Snyder
Inventor
Austin, TX, US
Overview
Patents· 47 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing80%
G11CStatic stores14%
G04FTime-interval measuring2%
G09BEducational or demonstration appliances2%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%
PatentTitleYear
9,395,983'Debug instruction for execution by a first thread to generate a debug event in a second thread to cause a halting operation'20169,213,665'Data processor for processing a decorated storage notify'20159,047,079'Indicating disabled thread to other threads when contending instructions complete execution to ensure safe shared resource condition'20159,026,742'System and method for processing potentially self-inconsistent memory transactions'20158,990,633'Tracing support for interconnect fabric'20158,972,671'Method and apparatus for cache transactions in a data processing system'20158,832,702'Thread de-emphasis instruction for multithreaded processor'20148,627,471'Permissions checking for data processing instructions'20148,615,644'Processor with hardware thread control logic indicating disable status when instructions accessing shared resources are completed for safe shared resource condition'20138,539,485'Polling using reservation mechanism'20138,531,899'Methods for testing a memory embedded in an integrated circuit'20138,379,466'Integrated circuit having an embedded memory and method for testing the memory'20138,380,779'Technique for determining if a logical sum of a first operand and a second operand is the same as a third operand'20138,261,047'Qualification of conditional debug instructions based on address'20128,199,547'Error detection in a content addressable memory (CAM)'20128,156,357'Voltage-based memory size scaling in a data processing system'20128,122,437'Method and apparatus to trace and correlate data trace and instruction trace for out-of-order processors'20128,117,618'Forward progress mechanism for a multithreaded processor'20128,041,901'Performance monitoring device and method thereof'20117,941,499'Interprocessor message transmission via coherency-based interconnect'20117,941,646'Completion continue on thread switch based on instruction progress metric mechanism for a microprocessor'20117,852,692'Memory operation testing'20107,849,247'Interrupt controller for accelerated interrupt handling in a data processing system and method thereof'20107,827,360'Cache locking device and methods thereof'20107,805,581'Multiple address and arithmetic bit-mode data processing device and methods thereof'20107,702,881'Method and system for data transfers across different address spaces'20107,688,656'Integrated circuit memory having dynamically adjustable read margin and method therefor'20107,689,815'Debug instruction for use in a data processing system'20107,681,021'Dynamic branch prediction using a wake value to enable low power mode for a predicted number of instruction fetches between a branch and a subsequent branch'20107,675,806'Low voltage memory device and method thereof'20107,506,105'Prefetching using hashed program counter'20097,069,384'System and method for cache external writing and write shadowing'20066,842,822'System and method for cache external writing'20056,785,772'Data prefetching apparatus in a data processing system and method therefor'20046,581,140'Method and apparatus for improving access time in set-associative cache systems'20036,499,116'Performance of data stream touch events'20026,321,303'Dynamically modifying queued transactions in a cache memory system'20016,311,254'Multiple store miss handling in a cache memory memory system'20016,269,427'Multiple load miss handling in a cache memory system'20016,240,479'Method and apparatus for transferring data on a split bus in a data processing system'20016,202,130'Data processing system for processing vector data and method therefor'20016,163,835'Method and apparatus for transferring data over a processor interface bus'20006,119,203'Mechanism for sharing data cache resources between data prefetch operations and normal load/store operations in a data processing system'20006,073,215'Data processing system having a data prefetch mechanism and method therefor'20005,630,095'Method for use with a data coherency protocol allowing multiple snoop queries to a single snoop transaction and system therefor'19975,422,914'System and method for synchronizing data communications between two devices operating at different clock frequencies'19954,193,064'Multiple pulse timer'1980Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1980–2016Patents assigned to SNYDER MICHAEL D (18)· patent assignee history
1980Based in Bridgewater, NJ, US· patent location history
1995–2003Patents assigned to MOTOROLA INC (9)· patent assignee history
1995–2015Based in Austin, TX, US· patent location history
2000–2015Patents assigned to IBM (7)· patent assignee history
2004–2016Patents assigned to FREESCALE SEMICONDUCTOR INC (31)· patent assignee history
2010–2016Based in Cedar Park, TX, US· patent location history
2012–2016Patents assigned to WHISENHUNT GARY L (7)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FREESCALE SEMICONDUCTOR INC | 31 | 2004–2016 |
| SNYDER MICHAEL Dself | 18 | 1980–2016 |
| MOTOROLA INC | 9 | 1995–2003 |
| IBM | 7 | 2000–2015 |
| WHISENHUNT GARY L | 7 | 2012–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 26 | 1995–2015 |
| Cedar Park, Texas, US | 20 | 2010–2016 |
| Bridgewater, New Jersey, US | 1 | 1980 |