Inventor
Kenneth D. Shoemaker
Inventor
Los Altos Hills, CA, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing41%
G11CStatic stores11%
H01LSemiconductor devices9%
H10BElectronic memory devices9%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h109%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use7%
G01KMeasuring temperature5%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications5%
B27FDovetailed work2%
B27MWorking of wood not provided for in subclasses b27b - b27l2%
PatentTitleYear
10,514,305Induced thermal gradients20199,916,876'Ultra low power architecture to support always on path to memory'20189,798,369'Indicating critical battery status in mobile devices'20179,768,148'Stacked memory with interface providing offset interconnects'20179,658,678'Induced thermal gradients'20179,627,357'Stacked memory allowing variance in device interconnects'20179,490,003'Induced thermal gradients'20169,396,787'Memory operations using system thermal sensor data'20169,384,351'Method and apparatus for implementing a secure boot using multiple firmware sources'20169,335,808'Indicating critical battery status in mobile devices'20169,104,540'Dynamic memory performance throttling'20158,971,087'Stacked memory with interface providing offset interconnects'20157,877,619'Power mode control method and circuitry'20117,685,451'Method and apparatus to limit current-change induced voltage changes in a microcircuit'20106,898,694'High instruction fetch bandwidth in multithread processor using temporary instruction cache to deliver portion of cache line in subsequent clock cycle'20056,088,793'Method and apparatus for branch execution on a multiple-instruction-set-architecture microprocessor'20006,082,421'Finger jointer'20006,055,652'Multiple segment register use with different operand size'20006,049,897'Multiple segment register use with different operand size'20005,978,900'Renaming numeric and segment registers using common general register pool'19995,802,605'Physical address size selection and page size selection in an address translator'19985,617,554'Physical address size selection and page size selection in an address translator'19975,586,276'End bit markers for indicating the end of a variable length instruction to facilitate parallel processing of sequential instructions'19965,475,824'Microprocessor with apparatus for parallel execution of instructions'19955,450,605'Boundary markers for indicating the boundary of a variable length instruction to facilitate parallel processing of sequential instructions'19955,179,679'Apparatus and method for permitting reading of data from an external memory when data is stored in a write buffer in the event of a cache read miss'19935,073,969'Microprocessor bus interface unit which changes scheduled data transfer indications upon sensing change in enable signals before receiving ready signal'1991Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1991–2019Patents assigned to INTEL CORP (24)· patent assignee history
1991–1998Based in Saratoga, CA, US· patent location history
1993–2017Patents assigned to SHOEMAKER KENNETH D (5)· patent assignee history
1995–2019Based in Los Altos Hills, CA, US· patent location history
1999Based in Los Altos, CA, US· patent location history
2000Based in Eugene, OR, US· patent location history
2011Patents assigned to CHOUBAL ASHISH V (1)· patent assignee history
2015–2017Patents assigned to SHOEMAKER KENNETH (4)· patent assignee history
2015–2017Patents assigned to VOGT PETE (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 24 | 1991–2019 |
| SHOEMAKER KENNETH Dself | 5 | 1993–2017 |
| SHOEMAKER KENNETHself | 4 | 2015–2017 |
| VOGT PETE | 2 | 2015–2017 |
| CHOUBAL ASHISH V | 1 | 2011 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Altos Hills, California, US | 19 | 1995–2019 |
| Saratoga, California, US | 6 | 1991–1998 |
| Eugene, OR, US | 1 | 2000 |
| Los Altos, California, US | 1 | 1999 |