Inventor

Chiakang Sung

Inventor

Milpitas, CA, US

Overview

1987–2017

Patent span

Electricity

Primary field (CPC H)

Patents· 194 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique40%

G11CStatic stores14%

H03LAutomatic control, starting, synchronisation or stabilisation of generators of electronic oscillations or pulses13%

G06FElectric digital data processing11%

G01RMeasuring electric variables5%

H04LTransmission of digital information, e.g. telegraphic communication5%

H03MCoding3%

H05KPrinted circuits1%

H10DInorganic electric semiconductor devices1%

A61KPreparations for medical, dental or toiletry purposes1%

PatentTitleYear

9,711,189'On-die input reference voltage with self-calibrating duty cycle correction'2017 9,558,131'Integrated circuit with bonding circuits for bonding memory controllers'2017 9,504,156'Distribution of return paths for improved impedance control and reduced crosstalk'2016 9,473,145'Programmable high-speed I/O interface'2016 9,208,109'Memory controllers with dynamic port priority assignment capabilities'2015 9,166,591'High speed IO buffer'2015 9,166,589'Multiple data rate interface architecture'2015 9,158,873'Circuit design technique for DQS enable/disable calibration'2015 9,111,603'Systems and methods for memory controller reference voltage calibration'2015 9,099,999'Adjustable drive strength input-output buffer circuitry'2015 9,048,823'Duty cycle distortion correction circuitry'2015 9,032,162'Systems and methods for providing memory controllers with memory access request merging capabilities'2015 9,001,595'Data strobe enable circuitry'2015 8,854,078'Dynamic termination-impedance control for bidirectional I/O pins'2014 8,829,948'Programmable high-speed I/O interface'2014 8,787,097'Circuit design technique for DQS enable/disable calibration'2014 8,779,754'Method and apparatus for minimizing skew between signals'2014 8,680,905'Digital PVT compensation for delay chain'2014 8,671,303'Write-leveling implementation in programmable logic devices'2014 8,630,131'Data strobe enable circuitry'2014 8,624,647'Duty cycle correction circuit for memory interfaces in integrated circuits'2014 8,610,462'Input-output circuit and method of improving input-output signals'2013 8,593,195'High performance memory interface circuit architecture'2013 8,575,957'Multiple data rate interface architecture'2013 8,565,034'Variation compensation circuitry for memory interface'2013 8,531,205'Programmable output buffer'2013 8,487,665'Programmable high-speed interface'2013 8,476,947'Duty cycle distortion correction circuitry'2013 8,400,186'Techniques for buffering single-ended and differential signals'2013 8,390,315'Configurable input-output (I/O) circuitry with pre-emphasis circuitry'2013 8,384,460'Techniques for phase adjustment'2013 8,368,449'Dead zone detection for phase adjustment'2013 8,305,121'High-performance memory interface circuit architecture'2012 8,237,475'Techniques for generating PVT compensated phase offset to improve accuracy of a locked loop'2012 8,159,277'Techniques for providing multiple delay paths in a delay circuit'2012 8,149,038'Techniques for phase adjustment'2012 8,130,016'Techniques for providing reduced duty cycle distortion'2012 8,122,275'Write-leveling implementation in programmable logic devices'2012 8,098,082'Multiple data rate interface architecture'2012 8,022,723'Dynamic termination-impedance control for bidirectional I/O pins'2011 7,994,821'Level shifter circuits and methods'2011 7,990,786'Read-leveling implementations for DDR3 applications on an FPGA'2011 7,973,553'Techniques for on-chip termination'2011 7,969,215'High-performance memory interface circuit architecture'2011 7,893,739'Techniques for providing multiple delay paths in a delay circuit'2011 7,884,619'Method and apparatus for minimizing skew between signals'2011 7,859,304'Multiple data rate interface architecture'2010 7,825,682'Techniques for providing adjustable on-chip termination impedance'2010 7,746,134'Digitally controlled delay-locked loops'2010 7,725,755'Self-compensating delay chain for multiple-date-rate interfaces'2010 7,710,149'Input buffer for multiple differential I/O standards'2010 7,706,996'Write-side calibration for data interface'2010 7,671,579'Method and apparatus for quantifying and minimizing skew between signals'2010 7,593,273'Read-leveling implementations for DDR3 applications on an FPGA'2009 7,589,556'Dynamic control of memory interface timing'2009 7,590,879'Clock edge de-skew'2009 7,586,341'Programmable high-speed interface'2009 7,551,014'Differential output with low output skew'2009 7,535,275'High-performance memory interface circuit architecture'2009 7,525,360'I/O duty cycle and skew control'2009 7,509,223'Read-side calibration for data interface'2009 7,492,185'Innovated technique to reduce memory interface write mode SSN in FPGA'2009 7,477,074'Multiple data rate interface architecture'2009 7,425,844'Input buffer for multiple differential I/O standards'2008 7,420,386'Techniques for providing flexible on-chip termination control on integrated circuits'2008 7,417,452'Techniques for providing adjustable on-chip termination impedance'2008 7,378,868'Modular I/O bank architecture'2008 7,358,783'Voltage, temperature, and process independent programmable phase shift for PLL'2008 7,330,051'Innovated technique to reduce memory interface write mode SSN in FPGA'2008 7,324,405'DQS postamble filtering'2008 7,321,518'Apparatus and methods for providing redundancy in integrated circuits'2008 7,315,188'Programmable high speed interface'2008 7,309,906'Apparatus and methods for providing highly effective and area efficient decoupling capacitance in programmable logic devices'2007 7,304,501'Method and apparatus for protecting a circuit during a hot socket condition'2007 7,295,040'High speed IO buffer using auxiliary power supply'2007 7,250,660'ESD protection that supports LVDS and OCT'2007 7,239,171'Techniques for providing multiple termination impedance values to pins on an integrated circuit'2007 7,236,018'Programmable low-voltage differential signaling output driver'2007 7,231,536'Control circuit for self-compensating delay chain for multiple-data-rate interfaces'2007 7,227,395'High-performance memory interface circuit architecture'2007 7,221,193'On-chip termination with calibrated driver strength'2007 7,218,155'Techniques for controlling on-chip termination resistance using voltage range detection'2007 7,215,143'Input buffer for multiple differential I/O standards'2007 7,212,054'DLL with adjustable phase shift using processed control signal'2007 7,205,788'Programmable on-chip differential termination impedance'2007 7,205,806'Loop circuitry with low-pass noise filter'2007 7,205,802'Apparatus and method for controlling a delay chain'2007 7,200,769'Self-compensating delay chain for multiple-date-rate interfaces'2007 7,196,556'Programmable logic integrated circuit devices with low voltage differential signaling capabilities'2007 7,190,755'Phase-locked loop circuitry for programmable logic devices'2007 7,167,023'Multiple data rate interface architecture'2007 7,148,722'PCI-compatible programmable logic devices'2006 7,119,579'Supply voltage detection circuit'2006 7,116,135'Programmable high speed I/O interface'2006 7,109,765'Programmable phase shift circuitry'2006 7,098,690'Programmable I/O element circuit for high speed logic devices'2006 7,091,760'DLL with adjustable phase shift using processed control signal'2006 7,088,140'High speed IO buffer using auxiliary power supply'2006 7,057,962'Address control for efficient memory partition'2006 7,046,037'Differential input buffers with elevated power supplies'2006 7,030,675'Apparatus and method for controlling a delay chain'2006 7,031,222'DQS postamble filtering'2006 7,026,847'Programmable current booster for faster edge-rate output in high speed applications'2006 7,002,384'Loop circuitry with low-pass noise filter'2006 6,992,947'Dual-port SRAM in a programmable logic device'2006 6,972,593'Method and apparatus for protecting a circuit during a hot socket condition'2005 6,970,024'Over-voltage protection of integrated circuit I/O pins'2005 6,961,280'Techniques for implementing address recycling in memory circuits'2005 6,956,401'Differential input buffers with elevated power supplies'2005 6,946,872'Multiple data rate interface architecture'2005 6,911,923'Data realignment techniques for serial-to-parallel conversion'2005 6,912,164'Techniques for preloading data into memory on programmable circuits'2005 6,911,860'On/off reference voltage switch for multiple I/O standards'2005 6,888,369'Programmable on-chip differential termination impedance'2005 6,870,400'Supply voltage detection circuit'2005 6,870,413'Schmitt trigger circuit with adjustable trip point voltages'2005 6,853,215'Programmable I/O element circuit for high speed logic devices'2005 6,836,164'Programmable phase shift circuitry'2004 6,825,698'Programmable high speed I/O interface'2004 6,825,692'Input buffer for multiple differential I/O standards'2004 RE038651'Variable depth and width memory device'2004 6,806,733'Multiple data rate interface architecture'2004 6,798,237'On-chip impedance matching circuit'2004 6,785,109'Technique for protecting integrated circuit devices against electrostatic discharge damage'2004 6,766,505'Parallel programming of programmable logic using register chains'2004 6,747,903'Configurable decoder for addressing a memory'2004 6,731,142'Circuit for providing clock signals with low skew'2004 6,731,137'Programmable, staged, bus hold and weak pull-up for bi-directional I/O'2004 6,714,044'Hi-speed parallel configuration of programmable logic'2004 6,707,399'Data realignment techniques for serial-to-parallel conversion'2004 6,691,267'Technique to test an integrated circuit using fewer pins'2004 6,686,769'Programmable I/O element circuit for high speed logic devices'2004 6,681,378'Programming mode selection with JTAG circuits'2004 6,670,825'Efficient arrangement of interconnection resources on programmable logic devices'2003 6,667,641'Programmable phase shift circuitry'2003 6,661,733'Dual-port SRAM in a programmable logic device'2003 6,646,467'PCI-compatible programmable logic devices'2003 6,642,758'Voltage, temperature, and process independent programmable phase shift for PLL'2003 6,630,844'Supply voltage detection circuit'2003 6,617,884'Fast locking phase frequency detector'2003 6,603,329'Systems and methods for on-chip impedance termination'2003 6,549,045'Circuit for providing clock signals with low skew'2003 6,538,469'Technique to test an integrated circuit using fewer pins'2003 6,535,031'Programmable logic integrated circuit devices with low voltage differential signaling capabilities'2003 6,507,216'Efficient arrangement of interconnection resources on programmable logic devices'2003 6,483,886'Phase-locked loop circuitry for programmable logic devices'2002 6,469,553'Phase-locked loop circuitry for programmable logic devices'2002 6,448,820'Fast locking phase frequency detector'2002 6,437,650'Phase-locked loop or delay-locked loop circuitry for programmable logic devices'2002 6,433,579'Programmable logic integrated circuit devices with differential signaling capabilities'2002 6,421,812'Programming mode selection with JTAG circuits'2002 6,400,598'Programmable logic integrated circuit devices with low voltage differential signaling capabilities'2002 6,384,629'High-speed programmable interconnect'2002 6,384,630'Techniques for programming programmable logic array devices'2002 6,373,278'LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device'2002 6,369,624'Programmable phase shift circuitry'2002 6,366,121'Programmable logic array integrated circuit architectures'2002 6,346,827'Programmable logic device input/output circuit configurable as reference voltage input circuit'2002 6,335,636'Programmable logic device input/output circuit configurable as reference voltage input circuit'2002 6,314,550'Cascaded programming with multiple-purpose pins'2001 6,292,116'Techniques and circuitry for accurately sampling high frequency data signals input to an integrated circuit'2001 6,271,729'Phase-locked loop or delay-locked loop circuitry for programmable logic devices'2001 6,271,681'PCI-compatible programmable logic devices'2001 6,262,595'High-speed programmable interconnect'2001 6,259,272'Programmable logic array integrated circuit architectures'2001 6,252,419'LVDS interface incorporating phase-locked loop circuitry for use in programmable logic device'2001 6,246,270'Innovated AC kicker for high speed low voltage swing differential output buffer with temperature compensation'2001 6,236,231'Programmable logic integrated circuit devices with low voltage differential signaling capabilities'2001 6,218,876'Phase-locked loop circuitry for programmable logic devices'2001 6,204,688'Programmable logic array integrated circuit devices with interleaved logic array blocks'2001 6,191,608'Techniques for programming programmable logic array devices'2001 RE037060'Apparatus for serial reading and writing of random access memory arrays'2001 6,177,844'Phase-locked loop or delay-locked loop circuitry for programmable logic devices'2001 6,127,844'PCI-compatible programmable logic devices'2000 6,128,692'Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices'2000 6,114,915'Programmable wide-range frequency synthesizer'2000 5,999,015'Logic region resources for programmable logic devices'1999 5,982,195'Programmable logic device architectures'1999 5,963,049'Programmable logic array integrated circuit architectures'1999 5,963,051'Segmented localized conductors for programmable logic devices'1999 5,915,017'Method and apparatus for securing programming data of programmable logic device'1999 5,909,126'Programmable logic array integrated circuit devices with interleaved logic array blocks'1999 5,892,683'Program compatibility recognition for a programmable logic device'1999 5,828,229'Programmable logic array integrated circuits'1998 5,802,540'Programming and verification address generation for random access memory blocks in programmable logic array integrated circuit devices'1998 5,768,372'Method and apparatus for securing programming data of a programmable logic device'1998 5,717,901'Variable depth and width memory device'1998 5,694,058'Programmable logic array integrated circuits with improved interconnection conductor utilization'1997 5,633,830'Random access memory block circuitry for programmable logic array integrated circuit devices'1997 5,555,214'Apparatus for serial reading and writing of random access memory arrays'1996 5,543,730'Techniques for programming programmable logic array devices'1996 5,028,814'Low power master-slave S/R flip-flop circuit'1991 4,841,176'Output disable control circuit for ECL programmable array logic device'1989 4,701,636'Programming voltage control circuit for programmable array logic device'1987

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1987–2017Based in San Jose, CA, US· patent location history

1991–2017Based in Milpitas, CA, US· patent location history

1996–2017Patents assigned to ALTERA CORP (190)· patent assignee history

2007Based in Milipitas, CA, US· patent location history

2012–2017Patents assigned to SUNG CHIAKANG (32)· patent assignee history

2012–2017Patents assigned to HUANG JOSEPH (21)· patent assignee history

2012–2017Patents assigned to CHONG YAN (15)· patent assignee history

2012–2017Patents assigned to NGUYEN KHAI (13)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ALTERA CORP	190	1996–2017
SUNG CHIAKANGself	32	2012–2017
HUANG JOSEPH	21	2012–2017
CHONG YAN	15	2012–2017
NGUYEN KHAI	13	2012–2017

Locations

Location	Patents	Span
Milpitas, California, US	190	1991–2017
San Jose, California, US	3	1987–2017
Milipitas, California, US	1	2007