Inventor

Eric E. Retter

Inventor

Austin, TX, US

Overview

70→

Patents

1993–2020

Patent span

Physics

Primary field (CPC G)

Patents· 70 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing59%

G11CStatic stores14%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use9%

F02BInternal-combustion piston engines5%

B04BCentrifuges2%

G04GElectronic time-pieces2%

G04RRadio-controlled time-pieces2%

H04NPictorial communication, e.g. television2%

G01RMeasuring electric variables1%

G09GArrangements or circuits for control of indicating devices using static means to present variable information1%

PatentTitleYear

10,713,169Remote node broadcast of requests in a multinode data processing system2020 10,649,511Scalable data collection for system management2020 10,387,310Remote node broadcast of requests in a multinode data processing system2019 10,317,964Scalable data collection for system management2019 10,176,125Dynamically adjusting read data return sizes based on interconnect bus utilization2019 9,892,066'Dynamically adjusting read data return sizes based on interconnect bus utilization'2018 9,684,461'Dynamically adjusting read data return sizes based on memory interface bus utilization'2017 9,665,346'Performing arithmetic operations using both large and small floating point values'2017 9,632,954'Memory queue handling techniques for reducing impact of high-latency memory operations'2017 9,594,647'Synchronization and order detection in a memory system'2017 9,495,254'Synchronization and order detection in a memory system'2016 9,477,550'ECC bypass using low latency CE correction with retry select signal'2016 9,471,410'Transient condition management utilizing a posted error detection processing protocol'2016 9,436,548'ECC bypass using low latency CE correction with retry select signal'2016 9,430,418'Synchronization and order detection in a memory system'2016 9,384,136'Modification of prefetch depth based on high latency event'2016 9,384,146'Dynamic reservations in a unified request queue'2016 9,378,144'Modification of prefetch depth based on high latency event'2016 9,361,240'Dynamic reservations in a unified request queue'2016 9,318,171'Dual asynchronous and synchronous memory system'2016 9,286,220'Provision of early data from a lower level cache memory'2016 9,250,666'Scalable data collection for system management'2016 9,176,877'Provision of early data from a lower level cache memory'2015 9,146,864'Address mapping including generic bits for universal addressing independent of memory type'2015 9,142,272'Dual asynchronous and synchronous memory system'2015 9,128,868'System for error decoding with retries and associated methods'2015 9,058,260'Transient condition management utilizing a posted error detection processing protocol'2015 9,037,811'Tagging in memory control unit (MCU)'2015 8,996,824'Memory reorder queue biasing preceding high latency operations'2015 8,990,641'Selective posted data error detection based on history'2015 8,990,643'Selective posted data error detection based on history'2015 8,984,041'Performing arithmetic operations using both large and small floating point values'2015 8,909,690'Performing arithmetic operations using both large and small floating point values'2014 8,909,874'Memory reorder queue biasing preceding high latency operations'2014 8,867,304'Command throttling for multi-channel duty-cycle based memory power management'2014 8,675,444'Synchronized command throttling for multi-channel duty-cycle based memory power management'2014 8,650,437'Computer system and method of protection for the system\'s marking store'2014 8,352,806'System to improve memory failure management and associated methods'2013 8,181,094'System to improve error correction using variable latency and associated methods'2012 8,176,391'System to improve miscorrection rates in error control code through buffering and associated methods'2012 8,139,430'Power-on initialization and test for a cascade interconnect memory system'2012 8,131,974'Access speculation predictor implemented via idle command processing resources'2012 8,127,106'Access speculation predictor with predictions based on a domain indicator of a cache line'2012 8,122,223'Access speculation predictor with predictions based on memory region prior requestor tag information'2012 8,122,222'Access speculation predictor with predictions based on a scope predictor'2012 8,103,900'Implementing enhanced memory reliability using memory scrub operations'2012 8,099,570'Methods, systems, and computer program products for dynamic selective memory mirroring'2012 7,793,143'Switching a defective signal line with a spare signal line without shutting down the computer system'2010 7,707,452'Recovering from errors in a data processing system'2010 7,661,008'Real time clock circuit having an internal clock generator'2010 7,587,559'Systems and methods for memory module power management'2009 7,571,357'Memory wrap test mode using functional read/write buffers'2009 7,493,456'Memory queue with supplemental locations for consecutive addresses'2009 7,421,598'Dynamic power management via DIMM read operation limiter'2008 7,409,580'System and method for recovering from errors in a data processing system'2008 7,380,161'Switching a defective signal line with a spare signal line without shutting down the computer system'2008 7,017,066'Method, system and synchronization circuit for providing hardware component access to a set of data values without restriction'2006 6,958,953'Real time clock circuit having an internal clock generator'2005 6,701,397'Pre-arbitration request limiter for an integrated multi-master bus system'2004 6,654,835'High bandwidth data transfer employing a multi-mode, shared line buffer'2003 6,611,159'Apparatus and method for synchronizing multiple circuits clocked at a divided phase locked loop frequency'2003 5,963,745'APAP I/O programmable router'1999 5,842,031'Advanced parallel array processor (APAP)'1998 5,717,943'Advanced parallel array processor (APAP)'1998 5,710,935'Advanced parallel array processor (APAP)'1998 5,625,836'SIMD/MIMD processing memory element (PME)'1997 5,617,577'Advanced parallel array processor I/O connection'1997 5,590,345'Advanced parallel array processor(APAP)'1996 5,252,209'Solid bowl worm centrifuge with improved discharge openings'1993 5,244,451'Method for operating a worm centrifuge having a pressurized gas introduction'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993Based in Cologne, DE· patent location history

1996–2020Patents assigned to IBM (66)· patent assignee history

1996–2004Based in Warren Center, PA, US· patent location history

2005–2020Based in Austin, TX, US· patent location history

2012–2017Patents assigned to RETTER ERIC E (16)· patent assignee history

2012–2017Patents assigned to STUECHELI JEFFREY A (8)· patent assignee history

2012–2015Patents assigned to LASTRAS-MONTANO LUIS A (6)· patent assignee history

2012–2014Patents assigned to WRIGHT KENNETH L (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	66	1996–2020
RETTER ERIC Eself	16	2012–2017
STUECHELI JEFFREY A	8	2012–2017
LASTRAS-MONTANO LUIS A	6	2012–2015
WRIGHT KENNETH L	6	2012–2014

Locations

Location	Patents	Span
Austin, Texas, US	58	2005–2020
Warren Center, Pennsylvania, US	10	1996–2004
Cologne, DE	2	1993