Inventor
Padmapani C. Nallan
Inventor
San Jose, CA, US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1042%
H10DInorganic electric semiconductor devices12%
H10NElectric solid-state devices not otherwise provided for8%
C23FNon-mechanical removal of metallic material from surface7%
B82YSpecific uses or applications of nanostructures5%
H01FMagnets5%
H01JElectric discharge tubes or discharge lamps5%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests5%
H10BElectronic memory devices3%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h103%
PatentTitleYear
7,838,434'Method of plasma etching of high-K dielectric materials'20107,320,942'Method for removal of metallic residue after plasma etching of a metal layer'20087,217,665'Method of plasma etching high-K dielectric materials with high selectivity to underlying layers'20077,105,361'Method of etching a magnetic material'20067,094,704'Method of plasma etching of high-K dielectric materials'20066,984,585'Method for removal of residue from a magneto-resistive random access memory (MRAM) film stack using a sacrificial mask layer'20066,964,928'Method for removing residue from a magneto-resistive random access memory (MRAM) film stack using a dual mask'20056,943,039'Method of etching ferroelectric layers'20056,942,813'Method of etching magnetic and ferroelectric materials using a pulsed bias source'20056,902,681'Method for plasma etching of high-K dielectric materials'20056,893,893'Method of preventing short circuits in magnetic film stacks'20056,855,643'Method for fabricating a gate structure'20056,806,095'Method of plasma etching of high-K dielectric materials with high selectivity to underlying layers'20046,767,824'Method of fabricating a gate structure of a field effect transistor using an alpha-carbon mask'20046,759,263'Method of patterning a layer of magnetic material'20046,759,340'Method of etching a trench in a silicon-on-insulator (SOI) structure'20046,759,286'Method of fabricating a gate structure of a field effect transistor using a hard mask'20046,660,127'Apparatus for plasma etching at a constant etch rate'20036,642,151'Techniques for plasma etching silicon-germanium'20036,642,127'Method for dicing a semiconductor wafer'20036,638,874'Methods used in fabricating gates in integrated circuit device structures'20036,583,065'Sidewall polymer forming gas additives for etching processes'20036,579,806'Method of etching tungsten or tungsten nitride in semiconductor structures'20036,531,404'Method of etching titanium nitride'20036,503,845'Method of etching a tantalum nitride layer in a high density plasma'20036,440,870'Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures'20026,423,644'Method of etching tungsten or tungsten nitride electrode gates in semiconductor structures'20026,415,198'Plasma etching of silicon using a chlorine chemistry augmented with sulfur dioxide'20026,399,507'Stable plasma process for etching of films'20026,368,978'Hydrogen-free method of plasma etching indium tin oxide'20026,322,714'Process for etching silicon-containing material on substrates'20016,132,631'Anisotropic silicon nitride etching for shallow trench isolation in an high density plasma system'20006,069,086'Non-HBr shallow trench isolation etch process'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2010Patents assigned to APPLIED MATERIALS INC (26)· patent assignee history
2000–2003Based in Sunnyvale, CA, US· patent location history
2002–2010Based in San Jose, CA, US· patent location history
2005Patents assigned to CHEN XIAOYI (1)· patent assignee history
2005Patents assigned to KUMAR AJAY (1)· patent assignee history
2005Patents assigned to NALLAN PADMAPANI C (1)· patent assignee history
2005Patents assigned to YING CHENTSAU (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| APPLIED MATERIALS INC | 26 | 2000–2010 |
| CHEN XIAOYI | 1 | 2005 |
| KUMAR AJAY | 1 | 2005 |
| NALLAN PADMAPANI Cself | 1 | 2005 |
| YING CHENTSAU | 1 | 2005 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 27 | 2002–2010 |
| Sunnyvale, California, US | 6 | 2000–2003 |