Inventor

William G. En

Inventor

Milpitas, CA, US

Overview

1999–2008

Patent span

Electricity

Primary field (CPC H)

Patents· 68 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices39%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1029%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%

H01JElectric discharge tubes or discharge lamps3%

B24BMachines, devices, or processes for grinding or polishing2%

G01RMeasuring electric variables2%

Y10TTechnical subjects covered by former us classification2%

C30BSingle-crystal growth1%

G01BMeasuring length, thickness or similar linear dimensions1%

PatentTitleYear

7,456,062'Method of forming a semiconductor device'2008 7,402,485'Method of forming a semiconductor device'2008 7,402,207'Method and apparatus for controlling the thickness of a selective epitaxial growth layer'2008 7,378,330'Cleaving process to fabricate multilayered substrates using low implantation doses'2008 7,298,012'Shallow junction semiconductor'2007 7,241,700'Methods for post offset spacer clean for improved selective epitaxy silicon growth'2007 7,211,473'Method and structure for controlling floating body effects'2007 7,132,683'Dual purpose test structure for gate-body current measurement in PD/SOI and for direct extraction of physical gate length in scaled CMOS technologies'2006 7,122,863'SOI device with structure for enhancing carrier recombination and method of fabricating same'2006 7,071,044'Method of making a test structure for gate-body current and direct extraction of physical gate length using conventional CMOS'2006 7,056,808'Cleaving process to fabricate multilayered substrates using low implantation doses'2006 7,033,916'Shallow junction semiconductor and method for the fabrication thereof'2006 6,964,875'Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance'2005 6,933,579'Semiconductor solid phase epitaxy damage control method and integrated circuit produced thereby'2005 6,905,971'Treatment of dielectric material to enhance etch rate'2005 6,867,130'Enhanced silicidation of polysilicon gate electrodes'2005 6,841,832'Array of gate dielectric structures to measure gate dielectric thickness and parasitic capacitance'2005 6,830,987'Semiconductor device with a silicon-on-void structure and method of making the same'2004 6,812,550'Wafer pattern variation of integrated circuit fabrication'2004 6,780,776'Nitride offset spacer to minimize silicon recess by using poly reoxidation layer as etch stop layer'2004 6,764,966'Spacers with a graded dielectric constant for semiconductor devices having a high-K dielectric'2004 6,764,917'SOI device with different silicon thicknesses'2004 6,764,898'Implantation into high-K dielectric material after gate etch to facilitate removal'2004 6,765,227'Semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer and method of fabrication using wafer bonding'2004 6,723,666'Method for reducing gate oxide surface irregularities'2004 6,717,212'Leaky, thermally conductive insulator material (LTCIM) in semiconductor-on-insulator (SOI) structure'2004 6,713,357'Method to reduce parasitic capacitance of MOS transistors'2004 6,713,819'SOI MOSFET having amorphized source drain and method of fabrication'2004 6,693,004'Interfacial barrier layer in semiconductor devices with high-K gate dielectric material'2004 6,611,023'Field effect transistor with self alligned double gate and method of forming same'2003 6,573,172'Methods for improving carrier mobility of PMOS and NMOS devices'2003 6,566,213'Method of fabricating multi-thickness silicide device formed by disposable spacers'2003 6,563,183'Gate array with multiple dielectric properties and method for forming same'2003 6,548,361'SOI MOSFET and method of fabrication'2003 6,534,381'Method for fabricating multi-layered substrates'2003 6,535,015'Device and method for testing performance of silicon structures'2003 6,518,631'Multi-Thickness silicide device formed by succesive spacers'2003 6,512,244'SOI device with structure for enhancing carrier recombination and method of fabricating same'2003 6,509,613'Self-aligned floating body control for SOI device through leakage enhanced buried oxide'2003 6,500,732'Cleaving process to fabricate multilayered substrates using low implantation doses'2002 6,492,830'Method and circuit for measuring charge dump of an individual transistor in an SOI device'2002 6,458,723'High temperature implant apparatus'2002 6,451,656'CMOS inverter configured from double gate MOSFET and method of fabricating same'2002 6,448,114'Method of fabricating a silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness'2002 6,441,433'Method of making a multi-thickness silicide SOI device'2002 6,433,391'Bonded SOI for floating body and metal gettering control'2002 6,414,355'Silicon-on-insulator (SOI) chip having an active layer of non-uniform thickness'2002 6,410,371'Method of fabrication of semiconductor-on-insulator (SOI) wafer having a Si/SiGe/Si active layer'2002 6,399,480'Methods and arrangements for insulating local interconnects for improved alignment tolerance and size reduction'2002 6,380,588'Semiconductor device having uniform spacers'2002 6,358,362'Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process'2002 6,303,949'Method and system for providing electrical insulation for local interconnect in a logic circuit'2001 6,297,167'In-situ etch of multiple layers during formation of local interconnects'2001 6,166,428'Formation of a barrier layer for tungsten damascene interconnects by nitrogen implantation of amorphous silicon or polysilicon'2000 6,121,663'Local interconnects for improved alignment tolerance and size reduction'2000 6,114,235'Multipurpose cap layer dielectric'2000 6,103,611'Methods and arrangements for improved spacer formation within a semiconductor device'2000 6,087,271'Methods for removal of an anti-reflective coating following a resist protect etching process'2000 6,066,567'Methods for in-situ removal of an anti-reflective coating during an oxide resistor protect etching process'2000 6,060,766'Protection of hydrogen sensitive regions in semiconductor devices from the positive charge associated with plasma deposited barriers or layers'2000 6,060,328'Methods and arrangements for determining an endpoint for an in-situ local interconnect etching process'2000 6,048,761'Method for manufacturing a semiconductor device with self-aligned protection diode'2000 6,027,959'Methods for in-situ removal of an anti-reflective coating during a nitride resistor protect etching process'2000 5,990,524'Silicon oxime spacer for preventing over-etching during local interconnect formation'1999 5,963,412'Process induced charging damage control device'1999 5,956,610'Method and system for providing electrical insulation for local interconnect in a logic circuit'1999 5,900,664'Semiconductor device with self-aligned protection diode'1999 5,895,269'Methods for preventing deleterious punch-through during local interconnect formation'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2008Patents assigned to ADVANCED MICRO DEVICES INC (63)· patent assignee history

1999–2008Based in Milpitas, CA, US· patent location history

1999–2002Based in Sunnyvale, CA, US· patent location history

2002–2008Patents assigned to SILICON GENESIS CORP (5)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
ADVANCED MICRO DEVICES INC	63	1999–2008
SILICON GENESIS CORP	5	2002–2008

Locations

Location	Patents	Span
Milpitas, California, US	55	1999–2008
Sunnyvale, California, US	13	1999–2002