Inventor
Jonathan H. Griffith
Inventor
Poughkeepsie, NY, US
Overview
Patents· 18 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1019%
Y02PClimate change mitigation technologies in the production or processing of goods8%
B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form6%
B81CProcesses or apparatus specially adapted for the manufacture or treatment of microstructural devices or systems6%
C23FNon-mechanical removal of metallic material from surface6%
H01LSemiconductor devices6%
Y10TTechnical subjects covered by former us classification6%
C03CChemical composition of glasses, glazes or vitreous enamels3%
C25DProcesses for the electrolytic or electrophoretic production of coatings3%
PatentTitleYear
10,049,909Wafer handler and methods of manufacture20189,613,842'Wafer handler and methods of manufacture'20178,807,184'Reduction of edge chipping during wafer handling'20148,753,460'Reduction of edge chipping during wafer handling'20148,314,500'Interconnections for flip-chip using lead-free solders and having improved reaction barrier layers'20127,932,169'Interconnection for flip-chip using lead-free solders and having improved reaction barrier layers'20117,767,575'Forming robust solder interconnect structures by reducing effects of seed layer underetching'20107,572,726'Method of forming a bond pad on an I/C chip and resulting structure'20097,473,997'Method for forming robust solder interconnect structures by reducing effects of seed layer underetching'20097,144,490'Method for selective electroplating of semiconductor device I/O pads using a titanium-tungsten seed layer'20066,995,084'Method for forming robust solder interconnect structures by reducing effects of seed layer underetching'20066,995,475'I/C chip suitable for wire bonding'20066,992,389'Barrier for interconnect and method'20066,531,069'Reactive Ion Etching chamber design for flip chip interconnections'20036,293,457'Integrated method for etching of BLM titanium-tungsten alloys for CMOS devices with copper metallization'20016,228,665'Method of measuring oxide thickness during semiconductor fabrication'20015,277,749'Methods and apparatus for relieving stress and resisting stencil delamination when performing lift-off processes that utilize high stress metals and/or multiple evaporation steps'19944,588,471'Process for etching composite chrome layers'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986–2017Patents assigned to IBM (15)· patent assignee history
1986–2018Based in Poughkeepsie, NY, US· patent location history
2006–2012Based in Lagrangeville, NY, US· patent location history
2012–2014Patents assigned to GRIFFITH JONATHAN H (2)· patent assignee history
2012Patents assigned to BELANGER LUC (1)· patent assignee history
2012Patents assigned to BUCHWALTER LEENA PAIVIKKI (1)· patent assignee history
2014Based in Hopewell Junction, NY, US· patent location history
2017–2018Patents assigned to GLOBALFOUNDRIES INC (2)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 15 | 1986–2017 |
| GLOBALFOUNDRIES INC | 2 | 2017–2018 |
| GRIFFITH JONATHAN Hself | 2 | 2012–2014 |
| BELANGER LUC | 1 | 2012 |
| BUCHWALTER LEENA PAIVIKKI | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Poughkeepsie, New York, US | 10 | 1986–2018 |
| Lagrangeville, New York, US | 7 | 2006–2012 |
| Hopewell Junction, New York, US | 1 | 2014 |