Inventor
Heonchul Park
Inventor
Cupertino, CA, US
Overview
Patents· 22 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing56%
G06TImage data processing or generation, in general6%
H04BTransmission6%
H04JMultiplex communication6%
H04WWireless communication networks6%
C01BNon-metallic elements3%
G01LMeasuring force, stress, torque, work, mechanical power, mechanical efficiency, or fluid pressure3%
G01RMeasuring electric variables3%
H01GCapacitors3%
H04NPictorial communication, e.g. television3%
PatentTitleYear
10,984,962Sensor and supercapacitor based on graphene polypyrrole 3D porous structure, and integrated device including the same20218,396,063'Multi-thread media access controller with per-thread MAC address'20137,761,688'Multiple thread in-order issue in-order completion DSP and micro-controller'20107,327,700'Flexible multi-channel multi-thread media access controller and physical layer interface for wireless networks'20086,865,590'Three input variable subfield comparation for fast matching'20056,529,033'Area efficient clock inverting circuit for design for testability'20036,401,194'Execution unit for processing a data stream independently and in parallel'20026,061,711'Efficient context saving and restoring in a multi-tasking computing system environment'20006,038,660'Method and apparatus for updating a program counter'20006,006,315'Computer methods for writing a scalar value to a vector'19995,991,531'Scalable width vector processor architecture for efficient emulation'19995,978,838'Coordination and synchronization of an asymmetric, single-chip, dual multiprocessor'19995,966,734'Resizable and relocatable memory scratch pad as a cache slice'19995,961,628'Load and store unit for a vector processor'19995,923,862'Processor that decodes a multi-cycle instruction into single-cycle micro-instructions and schedules execution of the micro-instructions'19995,922,066'Multifunction data aligner in wide data width processor'19995,889,986'Instruction fetch unit including instruction buffer and secondary or branch target buffer that transfers prefetched instructions to the instruction buffer'19995,881,307'Deferred store data read with simple anti-dependency pipeline inter-lock control in superscalar processor'19995,845,112'Method for performing dead-zone quantization in a single processor instruction'19985,838,984'Single-instruction-multiple-data processing using multiple banks of vector registers'19985,799,163'Opportunistic operand forwarding to minimize register file read ports'19985,468,069'Single chip design for fast image compression'1995Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1995–2021Based in Seoul, KR· patent location history
1998–2002Patents assigned to SAMSUNG ELECTRONICS CO LTD (13)· patent assignee history
1998–2013Based in Cupertino, CA, US· patent location history
2000–2003Patents assigned to INFINEON TECHNOLOGIES CORP (2)· patent assignee history
2000Based in Pleasanton, CA, US· patent location history
2005Patents assigned to INFINEON TECHNOLOGIES AG (1)· patent assignee history
2008–2013Patents assigned to REDPINE SIGNALS INC (3)· patent assignee history
2013Patents assigned to PARK HEONCHUL (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| SAMSUNG ELECTRONICS CO LTD | 13 | 1998–2002 |
| REDPINE SIGNALS INC | 3 | 2008–2013 |
| INFINEON TECHNOLOGIES CORP | 2 | 2000–2003 |
| INFINEON TECHNOLOGIES AG | 1 | 2005 |
| PARK HEONCHULself | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Cupertino, California, US | 19 | 1998–2013 |
| Seoul, KR | 2 | 1995–2021 |
| Pleasanton, California, US | 1 | 2000 |