Inventor

James Karp

Inventor

Saratoga, CA, US

Overview

1986–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 60 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices17%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1017%

H01LSemiconductor devices14%

H03KPulse technique12%

G06FElectric digital data processing10%

G11CStatic stores7%

H10BElectronic memory devices5%

Y10TTechnical subjects covered by former us classification3%

G01RMeasuring electric variables2%

H02HEmergency protective circuit arrangements2%

PatentTitleYear

10,901,097Method and apparatus for electronics-harmful-radiation (EHR) measurement and monitoring2021 10,861,848Single event latch-up (SEL) mitigation techniques2020 10,811,493Single event latch-up (SEL) mitigation techniques2020 10,636,869Mitigation for FinFET technology using deep isolation2020 10,522,531Integrated circuit device and method of transmitting data in an integrated circuit device2019 10,497,677ESD protection in a stacked integrated circuit assembly2019 10,325,901Circuit for increasing the impedance of an ESD path in an input/output circuit and method of implementing the same2019 10,289,178Configurable single event latch-up (SEL) and electrical overvoltage stress (EOS) detection circuit2019 10,015,916Removal of electrostatic charges from an interposer via a ground pad thereof for die attach for formation of a stacked die2018 9,960,227Removal of electrostatic charges from interposer for die attachment2018 9,831,218Wafer to wafer stacking2017 9,607,948'Method and circuits for communication in multi-die packages'2017 9,575,111'On chip detection of electrical overstress events'2017 9,548,738'High voltage RC-clamp for electrostatic discharge (ESD) protection'2017 9,484,919'Selection of logic paths for redundancy'2016 9,483,599'Circuit design-specific failure in time rate for single event upsets'2016 9,462,674'Circuits for and methods of providing a charge device model ground path using substrate taps in an integrated circuit device'2016 9,406,738'Inductive structure formed using through silicon vias'2016 9,378,322'Preparing layouts for semiconductor circuits'2016 9,379,109'Integrated circuit having improved radiation immunity'2016 9,275,180'Programmable integrated circuit having different types of configuration memory'2016 9,236,353'Integrated circuit having improved radiation immunity'2016 9,058,454'Method and apparatus to reduce power segmentation overhead within an integrated circuit'2015 9,058,853'Integrated circuit having improved radiation immunity'2015 9,013,844'Circuit for and method of enabling the discharge of electric charge in an integrated circuit'2015 9,013,845'High voltage RC-clamp for electrostatic discharge (ESD) protection'2015 9,000,529'Reduction of single event upsets within a semiconductor integrated circuit'2015 8,982,581'Electro-static discharge protection for die of a multi-chip module'2015 8,981,491'Memory array having improved radiation immunity'2015 8,947,839'Enhanced immunity from electrostatic discharge'2015 8,881,085'Cell-level electrostatic discharge protection for an integrated circuit'2014 8,866,229'Semiconductor structure for an electrostatic discharge protection circuit'2014 8,823,133'Interposer having an inductor'2014 8,519,741'Operating a programmable integrated circuit with functionally equivalent configuration bitstreams'2013 8,453,092'T-coil network design for improved bandwidth and electrostatic discharge immunity'2013 8,293,547'Hybrid integrated circuit device'2012 8,218,277'Shared electrostatic discharge protection for integrated circuit output drivers'2012 8,181,140'T-coil network design for improved bandwidth and electrostatic discharge immunity'2012 8,174,112'Integrated circuit device with low capacitance and high thermal conductivity interface'2012 8,134,813'Method and apparatus to reduce footprint of ESD protection within an integrated circuit'2012 8,079,002'Method and apparatus for evaluating paths in an integrated circuit design'2011 7,947,980'Non-volatile memory cell with charge storage element and method of programming'2011 7,919,845'Formation of a hybrid integrated circuit device'2011 7,812,674'Common centroid electrostatic discharge protection for integrated circuit devices'2010 7,812,642'Pass gate with improved latchup immunity'2010 7,687,797'Three-terminal non-volatile memory element with hybrid gate dielectric'2010 7,544,968'Non-volatile memory cell with charge storage element and method of programming'2009 7,450,431'PMOS three-terminal non-volatile memory element and method of programming'2008 7,420,842'Method of programming a three-terminal non-volatile memory element using source-drain bias'2008 7,002,219'Electrical fuse for integrated circuits'2006 6,740,936'Ballast resistor with reduced area for ESD protection'2004 6,638,852'Structure and method for preventing barrier failure'2003 6,549,458'Non-volatile memory array using gate breakdown structures'2003 6,522,582'Non-volatile memory array using gate breakdown structures'2003 6,432,808'Method of improved bondability when using fluorinated silicon glass'2002 6,316,132'Structure and method for preventing barrier failure'2001 6,266,269'Three terminal non-volatile memory element'2001 6,044,012'Non-volatile memory array using gate breakdown structure in standard sub 0.35 micron CMOS process'2000 5,796,070'Welding gun spatter shield'1998 4,567,652'Burn-in board loader'1986

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1986Based in Houston, TX, US· patent location history

1998Based in New Caney, TX, US· patent location history

2000–2021Patents assigned to XILINX INC (58)· patent assignee history

2000–2021Based in Saratoga, CA, US· patent location history

2011–2017Patents assigned to KARP JAMES (19)· patent assignee history

2011–2015Patents assigned to FAKHRUDDIN MOHAMMED (5)· patent assignee history

2012–2016Patents assigned to KIREEV VASSILI (5)· patent assignee history

2013–2016Patents assigned to HART MICHAEL J (6)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
XILINX INC	58	2000–2021
KARP JAMESself	19	2011–2017
HART MICHAEL J	6	2013–2016
FAKHRUDDIN MOHAMMED	5	2011–2015
KIREEV VASSILI	5	2012–2016

Locations

Location	Patents	Span
Saratoga, California, US	58	2000–2021
New Caney, Texas, US	1	1998
Houston, Texas, US	1	1986