Inventor

GILBERT DEWEY

Inventor

US

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 167 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices30%

H01LSemiconductor devices28%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1011%

B82YSpecific uses or applications of nanostructures10%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

H10BElectronic memory devices7%

H10NElectric solid-state devices not otherwise provided for2%

G06FElectric digital data processing0%

H03KPulse technique0%

H04LTransmission of digital information, e.g. telegraphic communication0%

PatentTitleYear

12,598,777Low temperature, high germanium, high boron SiGe:B pEPI with titanium silicide contacts for ultra-low PMOS contact resistivity and thermal stability2026 12,593,486Dual contact process with selective deposition2026 12,581,717Frontside and backside epi contact2026 12,575,184CMOS architecture with thermally stable silicide gate workfunction metal2026 12,575,170Low temperature, high germanium, high boron SiGe:B pEPI with a silicon rich capping layer for ultra-low PMOS contact resistivity and thermal stability2026 12,568,644Contact over active gate structures with trench contact layers for advanced integrated circuit structure fabrication2026 12,557,340Cladding and condensation for strained semiconductor nanoribbons2026 12,543,351Enriched semiconductor nanoribbons for producing intrinsic compressive strain2026 12,532,726Jumper gate for advanced integrated circuit structures2026 12,520,573SiGe:GAB source or drain structures with low resistivity2026 12,520,528Top-gate doped thin film transistor2026 12,457,778Conductive contacts wrapped around epitaxial source or drain regions2025 12,439,669Co-deposition of titanium and silicon for improved silicon germanium source and drain contacts2025 12,426,342Low germanium, high boron silicon rich capping layer for PMOS contact resistance thermal stability2025 12,414,339Formation of gate spacers for strained PMOS gate-all-around transistor structures2025 12,388,011Top gate recessed channel CMOS thin film transistor and methods of fabrication2025 12,369,399Gate-to-gate isolation for stacked transistor architecture via selective dielectric deposition structure2025 12,349,416Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures2025 12,342,574Contact resistance reduction in transistor devices with metallization on both sides2025 12,328,927Low resistance and reduced reactivity approaches for fabricating contacts and the resulting structures2025 12,288,803Transistor with isolation below source and drain2025 12,255,137Sideways vias in isolation areas to contact interior layers in stacked devices2025 12,224,202Forming an oxide volume within a fin2025 12,191,395Dual gate control for trench shaped thin film transistors2025 12,183,831Self-aligned contacts for thin film transistors2024 12,183,668Thin-film transistors and MIM capacitors in exclusion zones2024 12,183,739Ribbon or wire transistor stack with selective dipole threshold voltage shifter2024 12,170,319Dual contact process with stacked metal layers2024 12,148,806Stacked source-drain-gate connection and process for forming such2024 12,142,689Transistor including wrap around source and drain contacts2024 12,125,917Thin film transistors having double gates2024 12,120,865Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure2024 12,119,409Multi-layer crystalline back gated thin film transistor2024 12,119,387Low resistance approaches for fabricating contacts and the resulting structures2024 12,107,085Interconnect techniques for electrically connecting source/drain regions of stacked transistors2024 12,087,750Stacked-substrate FPGA semiconductor devices2024 12,080,605Backside contacts for semiconductor devices2024 12,068,319High performance semiconductor oxide material channel regions for NMOS2024 12,033,896Isolation wall stressor structures to improve channel stress and their methods of fabrication2024 12,020,929Epitaxial layer with substantially parallel sides2024 12,009,433Multi-dielectric gate stack for crystalline thin film transistors2024 11,996,411Stacked forksheet transistors2024 11,996,404Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material2024 11,996,447Field effect transistors with gate electrode self-aligned to semiconductor fin2024 11,997,847Thin film transistors with spacer controlled gate length2024 11,996,408Leave-behind protective layer having secondary purpose2024 11,990,476Semiconductor nanowire device having (111)-plane channel sidewalls2024 11,942,416Sideways vias in isolation areas to contact interior layers in stacked devices2024 11,935,891Non-silicon N-type and P-type stacked transistors for integrated circuit devices2024 11,929,435Ferroelectric gate stack for band-to-band tunneling reduction2024 11,929,320Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication2024 11,923,290Halogen treatment for NMOS contact resistance improvement2024 11,923,410Transistor with isolation below source and drain2024 11,916,118Stacked source-drain-gate connection and process for forming such2024 11,894,465Deep gate-all-around semiconductor device having germanium or group III-V active layer2024 11,895,824Vertical 1T-1C DRAM array2024 11,894,372Stacked trigate transistors with dielectric isolation and process for forming such2024 11,887,988Thin film transistor structures with regrown source and drain2024 11,869,894Metallization structures for stacked device connectivity and their methods of fabrication2024 11,869,890Stacked transistors with contact last2024 11,862,730Top-gate doped thin film transistor2024 11,862,728Dual gate control for trench shaped thin film transistors2024 11,843,058Transistor structures with a metal oxide contact buffer and a method of fabricating the transistor structures2023 11,843,054Vertical architecture of thin film transistors2023 11,837,648Stacked thin film transistors with nanowires2023 11,830,933Gate-all-around integrated circuit structures having depopulated channel structures using bottom-up oxidation approach2023 11,784,251Transistors with ferroelectric spacer and methods of fabrication2023 11,776,898Sidewall interconnect metallization structures for integrated circuit devices2023 11,777,013Channel formation for three dimensional transistors2023 11,764,263Gate-all-around integrated circuit structures having depopulated channel structures using multiple bottom-up oxidation approaches2023 11,764,282Antiferroelectric gate dielectric transistors and their methods of fabrication2023 11,764,275Indium-containing fin of a transistor device with an indium-rich core2023 11,764,306Multi-layer crystalline back gated thin film transistor2023 11,764,303Thin film transistors having double gates2023 11,764,104Forming an oxide volume within a fin2023 11,756,998Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)2023 11,742,346Interconnect techniques for electrically connecting source/drain regions of stacked transistors2023 11,721,735Thin film transistors having U-shaped features2023 11,699,704Monolithic integration of a thin film transistor over a complimentary transistor2023 11,695,081Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)2023 11,670,682FINFET transistor having a doped sub fin structure to reduce channel to substrate leakage2023 11,664,373Isolation walls for vertically stacked transistor structures2023 11,658,222Thin film transistor with charge trap layer2023 11,658,208Thin film transistors for high voltage applications2023 11,652,606Advanced encryption standard semiconductor devices fabricated on a stacked-substrate2023 11,646,352Stacked source-drain-gate connection and process for forming such2023 11,640,961III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts2023 11,631,737Ingaas epi structure and wet etch process for enabling III-v GAA in art trench2023 11,626,519Fabrication of non-planar IGZO devices for improved electrostatics2023 11,616,056Vertical diode in stacked transistor architecture2023 11,616,060Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure2023 11,605,565Three dimensional integrated circuits with stacked transistors2023 11,594,533Stacked trigate transistors with dielectric isolation between first and second semiconductor fins2023 11,588,102Semiconductor material for resistive random access memory2023 11,569,243Stacked-substrate DRAM semiconductor devices2023 11,569,238Vertical memory cells2023 11,563,119Etchstop regions in fins of semiconductor devices2023 11,557,658Transistors with high density channel semiconductor over dielectric material2023 11,538,803Integration of III-V transistors in a silicon CMOS stack2022 11,532,601Group III-N transistors for system on chip (SOC) architecture integrating power management and radio frequency circuits2022 11,532,719Transistors on heterogeneous bonding layers2022 11,532,619Transistor structures including a non-planar body having variable and complementary semiconductor and insulator portions2022 11,527,656Contact electrodes for vertical thin-film transistors2022 11,522,060Epitaxial layers on contact electrodes for thin- film transistors2022 11,508,577Channel layer formation for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)2022 11,482,621Vertically stacked CMOS with upfront M0 interconnect2022 11,476,366Transistor including wrap around source and drain contacts2022 11,476,338Aluminum indium phosphide subfin germanium channel transistors2022 11,469,323Ferroelectric gate stack for band-to-band tunneling reduction2022 11,462,568Stacked thin film transistors2022 11,450,750Thin-film transistors with vertical channels2022 11,444,159Field effect transistors with wide bandgap materials2022 11,437,405Transistors stacked on front-end p-type transistors2022 11,437,283Backside contacts for semiconductor devices2022 11,430,814Metallization structures for stacked device connectivity and their methods of fabrication2022 11,424,160Self-aligned local interconnects2022 11,424,335Group III-V semiconductor devices having dual workfunction gate electrodes2022 11,417,655High-mobility semiconductor source/drain spacer2022 11,417,770Vertical thin-film transistors between metal layers2022 11,411,119Double gated thin film transistors2022 11,398,479Heterogeneous Ge/III-V CMOS transistor structures2022 11,398,560Contact electrodes and dielectric structures for thin film transistors2022 11,398,478Semiconductor nanowire device having (111)-plane channel sidewalls2022 11,393,818Stacked transistors with Si PMOS and high mobility thin film transistor NMOS2022 11,393,722Isolation wall stressor structures to improve channel stress and their methods of fabrication2022 11,387,366Encapsulation layers of thin film transistors2022 11,387,238Non-silicon N-Type and P-Type stacked transistors for integrated circuit devices2022 11,380,797Thin film core-shell fin and nanowire transistors2022 11,380,684Stacked transistor architecture including nanowire or nanoribbon thin film transistors2022 11,374,024Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor2022 11,374,004Pedestal fin structure for stacked transistor integration2022 11,367,789Source/drain recess etch stop layers and bottom wide-gap cap for III-V MOSFETs2022 11,367,722Stacked nanowire transistor structure with different channel geometries for stress2022 11,362,215Top-gate doped thin film transistor2022 11,362,189Stacked self-aligned transistors with single workfunction metal2022 11,355,621Non-planar semiconductor device including a replacement channel structure2022 11,348,973Threshold switching selector based memory2022 11,348,916Leave-behind protective layer having secondary purpose2022 11,342,227Stacked transistor structures with asymmetrical terminal interconnects2022 11,342,327Stacked transistor layout2022 11,335,796Source to channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)2022 11,328,988Top gate recessed channel CMOS thin film transistor in the back end of line and methods of fabrication2022 11,309,400Stacked thin film transistors with nanowires2022 11,296,203Switching device having gate stack with low oxide growth2022 11,296,087Thin film transistors with spacer controlled gate length2022 11,296,229Vertical thin film transistors having self-aligned contacts2022 11,289,490Vertical 1T-1C DRAM array2022 11,276,755Field effect transistors with gate electrode self-aligned to semiconductor fin2022 11,276,694Transistor structure with indium phosphide channel2022 11,264,512Thin film transistors having U-shaped features2022 11,257,904Source-channel junction for III-V metal-oxide-semiconductor field effect transistors (MOSFETs)2022 11,257,956Thin film transistor with selectively doped oxide thin film2022 11,251,227Fully self-aligned cross grid vertical memory array2022 11,244,943Three-dimensional integrated circuits (3DICs) including bottom gate MOS transistors with monocrystalline channel material2022 11,239,232Isolation walls for vertically stacked transistor structures2022 11,205,707Optimizing gate profile for performance and gate fill2021 11,189,700Fabrication of wrap-around and conducting metal oxide contacts for IGZO non-planar devices2021 11,183,594Dual gate control for trench shaped thin film transistors2021 11,177,255Transistor structures having multiple threshold voltage channel materials2021 11,164,747Group III-V semiconductor devices having asymmetric source and drain structures2021 11,164,785Three-dimensional integrated circuits (3DICs) including upper-level transistors with epitaxial source and drain material2021 11,164,974Channel layer formed in an art trench2021 11,152,396Semiconductor device having stacked transistors and multiple threshold voltage control2021 11,152,514Multi-layer crystalline back gated thin film transistor2021 11,152,482Antiferroelectric gate dielectric transistors and their methods of fabrication2021 11,145,763Vertical switching device with self-aligned contact2021 11,139,296CMOS circuit with vertically oriented n-type transistor and method of providing same2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to INTEL CORP (165)· patent assignee history

2021–2026Based in US· patent location history

2024Patents assigned to GOOGLE LLC (1)· patent assignee history

2026Patents assigned to ACTON ORB (1)· patent assignee history

2026Patents assigned to DEWEY GILBERT (1)· patent assignee history

2026Patents assigned to HUANG CHENG YING (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
INTEL CORP	165	2021–2026
ACTON ORB	1	2026
DEWEY GILBERTself	1	2026
GOOGLE LLC	1	2024
HUANG CHENG YING	1	2026

Locations

Location	Patents	Span
US	167	2021–2026