Inventor
AARON D. LILAK
Inventor
US
Overview
Patents· 51 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices29%
H10DInorganic electric semiconductor devices28%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1015%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1013%
B82YSpecific uses or applications of nanostructures9%
H10BElectronic memory devices3%
G11CStatic stores1%
H10NElectric solid-state devices not otherwise provided for1%
G06FElectric digital data processing1%
H01FMagnets1%
PatentTitleYear
12,575,184CMOS architecture with thermally stable silicide gate workfunction metal202612,575,151Gate-all-around integrated circuit structures having doped subfin202612,538,470Structures and methods for memory cells202612,288,813Gate-all-around integrated circuit structures having insulator fin on insulator substrate202512,288,810Backside contact structures and fabrication for metal on both sides of devices202512,199,098Fin doping and integrated circuit structures resulting therefrom202512,107,085Interconnect techniques for electrically connecting source/drain regions of stacked transistors202412,080,605Backside contacts for semiconductor devices202412,057,494Stacked transistors202412,051,723PN-body-tied field effect transistors202412,033,896Isolation wall stressor structures to improve channel stress and their methods of fabrication202411,996,408Leave-behind protective layer having secondary purpose202411,935,933Backside contact structures and fabrication for metal on both sides of devices202411,894,262Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures202411,869,894Metallization structures for stacked device connectivity and their methods of fabrication202411,862,702Gate-all-around integrated circuit structures having insulator FIN on insulator substrate202411,784,239Subfin leakage suppression using fixed charge202311,742,346Interconnect techniques for electrically connecting source/drain regions of stacked transistors202311,699,637Vertically stacked transistor devices with isolation wall structures containing an electrical conductor202311,676,966Stacked transistors having device strata with different channel widths202311,672,133Vertically stacked memory elements with air gap202311,664,377Forksheet transistor architectures202311,658,221Backside contact structures and fabrication for metal on both sides of devices202311,658,072Vertically stacked transistors in a fin202311,658,183Metallization structures under a semiconductor device layer202311,640,961III-V source/drain in top NMOS transistors for low temperature stacked transistor contacts202311,616,056Vertical diode in stacked transistor architecture202311,616,060Techniques for forming gate structures for transistors arranged in a stacked configuration on a single fin structure202311,605,556Back side processing of integrated circuit structures to form insulation structure between adjacent transistor structures202311,573,798Stacked transistors with different gate lengths in different device strata202311,563,119Etchstop regions in fins of semiconductor devices202311,552,104Stacked transistors with dielectric between channels of different device strata202311,538,808Structures and methods for memory cells202211,444,148Recoiled metal thin film for 3D inductor with tunable core202211,437,283Backside contacts for semiconductor devices202211,430,814Metallization structures for stacked device connectivity and their methods of fabrication202211,424,160Self-aligned local interconnects202211,398,479Heterogeneous Ge/III-V CMOS transistor structures202211,393,818Stacked transistors with Si PMOS and high mobility thin film transistor NMOS202211,393,722Isolation wall stressor structures to improve channel stress and their methods of fabrication202211,374,004Pedestal fin structure for stacked transistor integration202211,374,024Integrated circuits with stacked transistors and methods of manufacturing the same using processes which fabricate lower gate structures following completion of portions of an upper transistor202211,348,916Leave-behind protective layer having secondary purpose202211,342,432Gate-all-around integrated circuit structures having insulator fin on insulator substrate202211,264,453Methods of doping fin structures of non-planar transistor devices202211,257,929Stacked transistors202211,257,738Vertically stacked transistor devices with isolation wall structures containing an electrical conductor202211,239,236Forksheet transistor architectures202211,222,947Methods of doping fin structures of non-planar transistor devices202211,201,221Backside contact structures and fabrication for metal on both sides of devices202111,152,396Semiconductor device having stacked transistors and multiple threshold voltage control2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2026Patents assigned to INTEL CORP (51)· patent assignee history
2021–2026Based in US· patent location history
2026Patents assigned to ACTON ORB (1)· patent assignee history
2026Patents assigned to DEWEY GILBERT (1)· patent assignee history
2026Patents assigned to HUANG CHENG YING (1)· patent assignee history
2026Patents assigned to KAVALIEROS JACK T (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 51 | 2021–2026 |
| ACTON ORB | 1 | 2026 |
| DEWEY GILBERT | 1 | 2026 |
| HUANG CHENG YING | 1 | 2026 |
| KAVALIEROS JACK T | 1 | 2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 51 | 2021–2026 |