Inventor
Mark E. Masters
Inventor
Essex Junction, VT, US
Overview
Patents· 17 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices17%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests17%
B82YSpecific uses or applications of nanostructures13%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%
G01RMeasuring electric variables8%
H10KOrganic electric solid-state devices8%
H10BElectronic memory devices7%
B01JChemical or physical processes, e.g. catalysis or colloid chemistry3%
G06FElectric digital data processing2%
PatentTitleYear
8,536,526'Methods of operating a nanoprober to electrically probe a device structure of an integrated circuit'20138,039,334'Shared gate for conventional planar device and horizontal CNT'20117,838,943'Shared gate for conventional planar device and horizontal CNT'20107,674,674'Method of forming a dual gated FinFET gain cell'20107,566,613'Method of forming a dual gated FinFET gain cell'20097,535,016'Vertical carbon nanotube transistor integration'20097,503,021'Integrated circuit diagnosing method, system, and program product'20097,484,423'Integrated carbon nanotube sensors'20097,473,633'Method for making integrated circuit chip having carbon nanotube composite interconnection vias'20097,247,877'Integrated carbon nanotube sensors'20077,135,773'Integrated circuit chip utilizing carbon nanotube composite interconnection vias'20067,109,546'Horizontal memory gain cells'20067,089,138'Canary device for failure analysis'20066,970,372'Dual gated finfet gain cell'20056,627,926'Method of designing and structure for visual and electrical test of semiconductor devices'20036,307,162'Integrated circuit wiring'20016,251,773'Method of designing and structure for visual and electrical test of semiconductor devices'2001Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2001–2013Patents assigned to IBM (17)· patent assignee history
2001–2013Based in Essex Junction, VT, US· patent location history
2013Patents assigned to BELL PAUL D (1)· patent assignee history
2013Patents assigned to MASTERS MARK E (1)· patent assignee history
2013Patents assigned to PATRICK DAVID S (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 17 | 2001–2013 |
| BELL PAUL D | 1 | 2013 |
| MASTERS MARK Eself | 1 | 2013 |
| PATRICK DAVID S | 1 | 2013 |
Locations
| Location | Patents | Span |
|---|---|---|
| Essex Junction, VT, US | 17 | 2001–2013 |