Inventor

Chester M. Nibby, Jr.

Inventor

Peabody, MA, US

Overview

1977–2001

Patent span

Physics

Primary field (CPC G)

Patents· 45 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary

G06FElectric digital data processing68%

G11CStatic stores20%

H05KPrinted circuits3%

H03HImpedance networks, e.g. resonant circuits2%

H03MCoding2%

H04LTransmission of digital information, e.g. telegraphic communication2%

Y02EReduction of greenhouse gas [ghg] emissions, related to energy generation, transmission or distribution2%

Y10TTechnical subjects covered by former us classification2%

PatentTitleYear

6,311,286'Symmetric multiprocessing system with unified environment and distributed system functions'2001 6,125,436'Symmetric multiprocessing system with unified environment and distributed system functions wherein bus operations related storage spaces are mapped into a single system address space'2000 5,956,522'Symmetric multiprocessing system with unified environment and distributed system functions'1999 5,809,340'Adaptively generating timing signals for access to various memory devices based on stored profiles'1998 5,522,069'Symmetric multiprocessing system with unified environment and distributed system functions'1996 5,517,648'Symmetric multiprocessing system with unified environment and distributed system functions'1996 5,491,790'Power-on sequencing apparatus for initializing and testing a system processing unit'1996 5,379,378'Data processing system having a bus command generated by one subsystem on behalf of another subsystem'1995 5,345,573'High speed burst read address generation with high speed transfer'1994 5,341,501'Processor bus access'1994 5,291,580'High performance burst read data transfer operation'1994 4,916,601'Means for transferring firmware signals between a control store and a microprocessor means through a reduced number of connections by transfer according to firmware signal function'1990 4,910,666'Apparatus for loading and verifying a control store memory of a central subsystem'1990 4,833,601'Cache resiliency in processing a variety of address faults'1989 4,799,222'Address transform method and apparatus for transferring addresses'1989 4,558,429'Pause apparatus for a memory controller with interleaved queuing apparatus'1985 4,545,010'Memory identification apparatus and method'1985 4,527,251'Remap method and apparatus for a memory system which uses partially good memory devices'1985 4,523,313'Partial defective chip memory support system'1985 4,507,730'Memory system with automatic memory configuration'1985 4,468,731'Identification apparatus for use in a controller to facilitate the diagnosis of faults'1984 4,451,880'Memory controller with interleaved queuing apparatus'1984 4,432,055'Sequential word aligned addressing apparatus'1984 4,388,684'Apparatus for deferring error detection of multibyte parity encoded data received from a plurality of input/output data sources'1983 4,376,972'Sequential word aligned address apparatus'1983 4,370,712'Memory controller with address independent burst mode capability'1983 4,369,510'Soft error rewrite control system'1983 4,366,539'Memory controller with burst mode capability'1982 4,366,538'Memory controller with queue control apparatus'1982 4,361,869'Multimode memory system using a multiword common bus for double word and single word transfer'1982 4,359,771'Method and apparatus for testing and verifying the operation of error control apparatus within a memory'1982 4,323,965'Sequential chip select decode apparatus and method'1982 4,319,324'Double word fetch system'1982 4,317,169'Data processing system having centralized memory refresh'1982 4,303,993'Memory present apparatus'1981 4,302,735'Delay line compensation network'1981 4,296,467'Rotating chip selection technique and apparatus'1981 4,255,852'Method of constructing a number of different memory systems'1981 4,236,203'System providing multiple fetch bus cycle operation'1980 4,190,901'Printed circuit board apparatus which facilitates fabrication of units comprising a data processing system'1980 4,185,323'Dynamic memory system which includes apparatus for performing refresh operations in parallel with normal memory operations'1980 4,077,565'Error detection and correction locator circuits'1978 4,072,853'Apparatus and method for storing parity encoded data from a plurality of input/output sources'1978 4,060,794'Apparatus and method for generating timing signals for latched type memories'1977 4,044,330'Power strobing to achieve a tri state'1977

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1977–1985Patents assigned to HONEYWELL INF SYSTEMS (30)· patent assignee history

1977–1985Based in Peabody, MA, US· patent location history

1989–1996Patents assigned to BULL HN INFORMATION SYST (8)· patent assignee history

1989–2001Based in Beverly, MA, US· patent location history

1996Patents assigned to ZENITH DATA SYSTEMS CORP (2)· patent assignee history

1998–1999Patents assigned to PACKARD BELL NEC (2)· patent assignee history

2000–2001Patents assigned to NEC CORP (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
HONEYWELL INF SYSTEMS	30	1977–1985
BULL HN INFORMATION SYST	8	1989–1996
NEC CORP	2	2000–2001
PACKARD BELL NEC	2	1998–1999
ZENITH DATA SYSTEMS CORP	2	1996

Locations

Location	Patents	Span
Peabody, Massachusetts, US	30	1977–1985
Beverly, Massachusetts, US	15	1989–2001