Inventor

Raymond Marcelino Manese Lim

Inventor

Los Altos Hills, CA, US

Overview

2002–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H04Lprimary

H04LTransmission of digital information, e.g. telegraphic communication48%

G06FElectric digital data processing30%

H04QSelecting18%

H01LSemiconductor devices1%

H10DInorganic electric semiconductor devices1%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h101%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h101%

PatentTitleYear

11,037,851Nitrogen-rich silicon nitride films for thin film transistors2021 9,912,590'In-line packet processing'2018 9,817,773'System and method for preserving order of data processed by processing engines'2017 9,479,436'In-line packet processing'2016 9,411,776'Separation of data and control in a switching device'2016 9,361,225'Centralized memory allocation with write pointer drift correction'2016 9,178,840'Systems and methods for preserving the order of data'2015 8,880,808'Centralized memory allocation with write pointer drift correction'2014 8,867,543'In-line packet processing'2014 8,761,180'Memory organization in a network device'2014 8,706,896'Guaranteed bandwidth memory apparatus and method'2014 8,681,796'Separation of data and control in a switching device'2014 8,477,784'Memory organization in a switching device'2013 8,397,233'Systems and methods for preserving the order of data'2013 8,271,672'Guaranteed bandwidth memory apparatus and method'2012 8,233,496'Systems and methods for efficient multicast handling'2012 8,189,605'Separation of data and control in a switching device'2012 8,085,780'Optimized buffer loading for packet header processing'2011 8,077,724'In-line packet processing'2011 8,014,281'Systems and methods for limiting the rates of data to/from a buffer'2011 7,983,278'Redirect checking in a network device'2011 7,936,758'Logical separation and accessing of descriptor memories'2011 7,916,632'Systems and methods for handling packet fragmentation'2011 7,903,659'Memory organization in a switching device'2011 7,859,999'Memory load balancing for single stream multicast'2010 7,804,833'In-line packet processing'2010 7,801,140'In-line packet processing'2010 7,782,857'Logical separation and accessing of descriptor memories'2010 7,773,599'Packet fragment handling'2010 7,724,737'Systems and methods for memory utilization during packet forwarding'2010 7,710,994'Systems and methods for efficient multicast handling'2010 7,680,116'Optimized buffer loading for packet header processing'2010 7,630,309'Systems and methods for limiting the rates of data to/from a buffer'2009 7,616,562'Systems and methods for handling packet fragmentation'2009 7,545,808'Memory organization in a switching device'2009 7,489,699'Separation of data and control in a switching device'2009 7,421,564'Incrementing successive write operations to a plurality of memory devices'2008 7,317,721'Systems and methods for memory utilization during packet forwarding'2008 7,292,529'Memory load balancing for single stream multicast'2007 7,289,503'Systems and methods for efficient multicast handling'2007 7,283,528'On the fly header checksum processing using dedicated logic'2007 7,240,347'Systems and methods for preserving the order of data'2007 7,239,630'Dedicated processing resources for packet header generation'2007 7,236,501'Systems and methods for handling packet fragmentation'2007 7,215,662'Logical separation and accessing of descriptor memories'2007 7,212,530'Optimized buffer loading for packet header processing'2007 7,209,448'In-line packet processing'2007 7,180,893'Parallel layer 2 and layer 3 processing components in a network router'2007 7,158,520'Mailbox registers for synchronizing header processing execution'2007 7,116,660'Memory organization in a switching device'2006 7,106,696'Systems and methods for limiting the rates of data to/from a buffer'2006 7,082,134'Redirect checking in a network device'2006 7,032,082'Centralized memory allocation with write pointer drift correction'2006 6,941,433'Systems and methods for memory read response latency detection'2005 6,917,620'Separation of data and control in a switching device'2005 6,791,947'In-line packet processing'2004 6,636,952'Systems and methods for processing packet streams in a network device'2003 6,493,347'Memory organization in a switching device'2002

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2002–2018Patents assigned to JUNIPER NETWORKS INC (55)· patent assignee history

2002–2014Based in Mountain View, CA, US· patent location history

2005–2016Based in Los Altos Hills, CA, US· patent location history

2007–2014Patents assigned to LIM RAYMOND MARCELINO MANESE (8)· patent assignee history

2011–2014Patents assigned to VEERAGANDHAM SREERAM (6)· patent assignee history

2011–2014Patents assigned to FERGUSON DENNIS C (5)· patent assignee history

2011–2014Patents assigned to JU HANN-HWAN (5)· patent assignee history

2016–2018Based in Scarsdale, NY, US· patent location history

2021Based in Daly City, CA, US· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
JUNIPER NETWORKS INC	55	2002–2018
LIM RAYMOND MARCELINO MANESEself	8	2007–2014
VEERAGANDHAM SREERAM	6	2011–2014
FERGUSON DENNIS C	5	2011–2014
JU HANN-HWAN	5	2011–2014

Locations

Location	Patents	Span
Los Altos Hills, California, US	36	2005–2016
Mountain View, California, US	17	2002–2014
Scarsdale, New York, US	4	2016–2018
Daly City, California, US	1	2021