Inventor
Steven R. Sherman
Inventor
Newton, MA, US
Overview
Patents· 20 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H01LSemiconductor devices19%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
H01JElectric discharge tubes or discharge lamps10%
H10DInorganic electric semiconductor devices9%
H10BElectronic memory devices6%
C23CCoating metallic material4%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices4%
G11CStatic stores3%
H10NElectric solid-state devices not otherwise provided for3%
PatentTitleYear
10,777,414Methods for reducing transfer pattern defects in a semiconductor device202010,629,437Techniques and structure for forming dynamic random-access device using angled ions202010,332,748Etch rate modulation through ion implantation201910,310,379Multiple patterning approach using ion implantation201910,229,832Techniques for forming patterned features using directional ions201910,204,909Non-uniform gate oxide thickness for DRAM device20199,934,981Techniques for processing substrates using directional reactive ion etching20189,934,982Etch rate modulation through ion implantation20189,728,623'Replacement metal gate transistor'20179,613,813'Method for improving critical dimension variability by implanting argon or silicon ions into a patterned mask'20179,153,444'Process flow for replacement metal gate transistors'20159,082,949'Magnetic memory and method of fabrication'20158,946,836'Magnetic memory and method of fabrication'20158,192,805'Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices'20127,981,483'Method to improve electrical leakage performance and to minimize electromigration in semiconductor devices'20117,838,423'Method of forming capping structures on one or more material layer surfaces'20107,799,683'Copper interconnect wiring and method and apparatus for forming thereof'20107,754,588'Method to improve a copper/dielectric interface in semiconductor devices'20107,291,558'Copper interconnect wiring and method of forming thereof'20076,919,061'In-situ method for treating residual sodium'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005Based in Idaho Falls, ID, US· patent location history
2007–2012Patents assigned to TEL EPION INC (6)· patent assignee history
2007Based in Waltham, MA, US· patent location history
2010–2020Based in Newton, MA, US· patent location history
2012Patents assigned to HAUTALA JOHN J (1)· patent assignee history
2015Patents assigned to VARIAN SEMICONDUCTOR EQUIPMENT (3)· patent assignee history
2017–2020Patents assigned to VARIAN SEMICONDUCTOR EQUIPMENT ASS INC (9)· patent assignee history
2020Patents assigned to APPLIED MATERIALS INC (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| VARIAN SEMICONDUCTOR EQUIPMENT ASS INC | 9 | 2017–2020 |
| TEL EPION INC | 6 | 2007–2012 |
| VARIAN SEMICONDUCTOR EQUIPMENT | 3 | 2015 |
| APPLIED MATERIALS INC | 1 | 2020 |
| HAUTALA JOHN J | 1 | 2012 |
Locations
| Location | Patents | Span |
|---|---|---|
| Newton, Massachusetts, US | 18 | 2010–2020 |
| Waltham, Massachusetts, US | 1 | 2007 |
| Idaho Falls, ID, US | 1 | 2005 |