Inventor

Chi-Lin Liu

Inventor

New Taipei, TW

Overview

21→

Patents

2013–2020

Patent span

Electricity

Primary field (CPC H)

Patents· 21 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H03Kprimary

H03KPulse technique30%

H10DInorganic electric semiconductor devices17%

G06FElectric digital data processing15%

G01RMeasuring electric variables13%

H01LSemiconductor devices13%

G11CStatic stores4%

H03MCoding2%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h102%

Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use2%

Y02PClimate change mitigation technologies in the production or processing of goods2%

PatentTitleYear

10,824,784System and method of timing characterization for semiconductor circuit2020 10,691,849Metal cut optimization for standard cells2020 10,686,428Cell of transmission gate free circuit and integrated circuit layout including the same2020 10,685,162Layout for integrated circuit and the integrated circuit2020 10,664,565Method and system of expanding set of standard cells which comprise a library2020 10,530,345Flip-flop with delineated layout for reduced footprint2020 10,382,018Flip flop circuit and method of operating the same2019 10,326,430Low power flip flop circuit2019 10,270,430Cell of transmission gate free circuit and integrated circuit and integrated circuit layout including the same2019 10,270,432Flip-flop with delineated layout for reduced footprint2019 10,163,883Layout method for integrated circuit and layout of the integrated circuit2018 10,003,342Compressor circuit and compressor circuit layout2018 9,887,698'Internal clock gated cell'2018 9,853,630Skew-tolerant flip-flop2017 9,641,161'Flip-flop with delineated layout for reduced footprint'2017 9,584,099'Flip flop circuit'2017 9,356,583'Flip-flop circuit'2016 9,203,405'Low-power internal clock gated cell and method'2015 8,575,965'Internal clock gating apparatus'2013 8,416,002'Flip-flop circuit design'2013 8,359,528'Parity look-ahead scheme for tag cache memory'2013

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2013–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (4)· patent assignee history

2013Patents assigned to CHOU CHUNG-CHENG (3)· patent assignee history

2013Patents assigned to LIU CHI-LIN (3)· patent assignee history

2013Patents assigned to CHEN YI-TZU (2)· patent assignee history

2013Based in Yonghe City, TW· patent location history

2015–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (17)· patent assignee history

2015–2020Based in New Taipei, TW· patent location history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
TAIWAN SEMICONDUCTOR MFG CO LTD	17	2015–2020
TAIWAN SEMICONDUCTOR MFG	4	2013–2016
CHOU CHUNG-CHENG	3	2013
LIU CHI-LINself	3	2013
CHEN YI-TZU	2	2013

Locations

Location	Patents	Span
New Taipei, TW	18	2015–2020
Yonghe City, TW	3	2013