Inventor
Anthony M. Petro
Inventor
Austin, TX, US
Overview
Patents· 27 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing39%
G11CStatic stores30%
H03KPulse technique30%
PatentTitleYear
6,911,846'Method and apparatus for a 1 of N signal'20056,571,378'Method and apparatus for a N-NARY logic circuit using capacitance isolation'20036,347,327'Method and apparatus for N-nary incrementor'20026,334,183'Method and apparatus for handling partial register accesses'20016,334,136'Dynamic 3-level partial result merge adder'20016,324,239'Method and apparatus for a 1 of 4 shifter'20016,301,600'Method and apparatus for dynamic partitionable saturating adder/subtractor'20016,301,597'Method and apparatus for saturation in an N-NARY adder/subtractor'20016,288,589'Method and apparatus for generating clock signals'20016,275,841'1-of-4 multiplier'20016,272,514'Method and apparatus for interruption of carry propagation on partition boundaries'20016,269,387'Method and apparatus for 3-stage 32-bit adder/subtractor'20016,268,746'Method and apparatus for logic synchronization'20016,252,425'Method and apparatus for an N-NARY logic circuit'20016,233,707'Method and apparatus that allows the logic state of a logic gate to be tested when stopping or starting the logic gate\'s clock'20016,223,199'Method and apparatus for an N-NARY HPG gate'20016,219,687'Method and apparatus for an N-nary Sum/HPG gate'20016,219,686'Method and apparatus for an N-NARY sum/HPG adder/subtractor gate'20016,216,147'Method and apparatus for an N-nary magnitude comparator'20016,216,146'Method and apparatus for an N-nary adder gate'20016,154,120'Method and apparatus for an N-nary equality comparator'20006,124,735'Method and apparatus for a N-nary logic circuit using capacitance isolation'20006,118,304'Method and apparatus for logic synchronization'20006,107,835'Method and apparatus for a logic circuit with constant power consumption'20006,069,497'Method and apparatus for a N-nary logic circuit using 1 of N signals'20006,066,965'Method and apparatus for a N-nary logic circuit using 1 of 4 signals'20006,032,252'Apparatus and method for efficient loop control in a superscalar microprocessor'2000Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2000–2005Patents assigned to INTRINSITY INC (23)· patent assignee history
2000Patents assigned to EVSX INC (3)· patent assignee history
2000Patents assigned to ADVANCED MICRO DEVICES INC (1)· patent assignee history
2000–2005Based in Austin, TX, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTRINSITY INC | 23 | 2000–2005 |
| EVSX INC | 3 | 2000 |
| ADVANCED MICRO DEVICES INC | 1 | 2000 |
Locations
| Location | Patents | Span |
|---|---|---|
| Austin, Texas, US | 27 | 2000–2005 |