Inventor
Todd P. Lukanc
Inventor
San Jose, CA, US
Overview
Patents· 72 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1023%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1021%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices20%
H10DInorganic electric semiconductor devices18%
G06FElectric digital data processing10%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%
B24BMachines, devices, or processes for grinding or polishing1%
H01JElectric discharge tubes or discharge lamps1%
H01LSemiconductor devices1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
PatentTitleYear
9,274,410'Method and system for automated generation of masks for spacer formation from a desired final wafer pattern'20169,064,078'Methods and systems for designing and manufacturing optical lithography masks'20158,975,195'Methods for optical proximity correction in the design and fabrication of integrated circuits'20158,003,545'Method of forming an electronic device including forming features within a mask and a selective removal process'20117,657,864'System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques'20107,543,256'System and method for designing an integrated circuit device'20097,487,492'Method for increasing manufacturability of a circuit layout'20097,368,225'Two mask photoresist exposure pattern for dense and isolated regions'20087,313,769'Optimizing an integrated circuit layout by taking into consideration layout interactions as well as extra manufacturability margin'20077,269,804'System and method for integrated circuit device design and manufacture using optical rule checking to screen resolution enhancement techniques'20077,207,017'Method and system for metrology recipe generation and review and analysis of design, simulation and metrology results'20077,194,725'System and method for design rule creation and selection'20077,108,946'Method of lithographic image alignment for use with a dual mask exposure technique'20067,076,750'Method and apparatus for generating trenches for vias'20067,071,085'Predefined critical spaces in IC patterning to reduce line end pull back'20067,027,130'Device and method for determining an illumination intensity profile of an illuminator for a lithography system'20067,015,148'Reduce line end pull back by exposing and etching space after mask one trim and etch'20066,995,433'Microdevice having non-linear structural component and method of fabrication'20066,974,652'Lithographic photomask and method of manufacture to improve photomask test measurement'20056,818,358'Method of extending the areas of clear field phase shift generation'20046,803,178'Two mask photoresist exposure pattern for dense and isolated regions'20046,797,438'Method and enhancing clear field phase shift masks with border around edges of phase regions'20046,768,204'Self-aligned conductive plugs in a semiconductor device'20046,753,266'Method of enhancing gate patterning properties with reflective hard mask'20046,749,971'Method of enhancing clear field phase shift masks with chrome border around phase 180 regions'20046,749,970'Method of enhancing clear field phase shift masks with border regions around phase 0 and phase 180 regions'20046,689,541'Process for forming a photoresist mask'20046,675,369'Method of enhancing clear field phase shift masks by adding parallel line to phase 0 region'20046,660,645'Process for etching an organic dielectric using a silyated photoresist mask'20036,641,747'Method and apparatus for determining an etch endpoint'20036,635,409'Method of strengthening photoresist to prevent pattern collapse'20036,633,083'Barrier layer integrity test'20036,615,400'Optimizing dense via arrays of shrunk integrated circuit designs'20036,566,214'Method of making a semiconductor device by annealing a metal layer to form metal silicide and using the metal silicide as a hard mask to pattern a polysilicon layer'20036,563,221'Connection structures for integrated circuits and processes for their formation'20036,548,423'Multilayer anti-reflective coating process for integrated circuit fabrication'20036,534,224'Phase shift mask and system and method for making the same'20036,528,372'Sidewall spacer definition of gates'20036,524,947'Slotted trench dual inlaid structure and method of forming thereof'20036,516,450'Variable design rule tool'20036,514,802'Method of providing a frontside contact to a substrate of SOI device'20036,479,350'Reduced masking step CMOS transistor formation using removable amorphous silicon sidewall spacers'20026,472,317'Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers'20026,458,606'Etch bias distribution across semiconductor wafer'20026,448,164'Dark field image reversal for gate or line patterning'20026,383,827'Electrical alignment test structure using local interconnect ladder resistor'20026,358,856'Bright field image reversal for contact hole patterning'20026,355,511'Method of providing a frontside contact to substrate of SOI device'20026,350,687'Method of fabricating improved copper metallization including forming and removing passivation layer before forming capping film'20026,312,874'Method for forming a dual damascene trench and underlying borderless via in low dielectric constant materials'20016,309,955'Method for using a CVD organic barc as a hard mask during via etch'20016,291,860'Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and silicides'20016,291,887'Dual damascene arrangements for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer'20016,279,147'Use of an existing product map as a background for making test masks'20016,265,253'Aluminum disposable spacer to reduce mask count in CMOS transistor formation'20016,262,435'Etch bias distribution across semiconductor wafer'20016,255,735'Dual damascene arrangement for metal interconnection with low k dielectric constant materials in dielectric layers'20016,221,706'Aluminum disposable spacer to reduce mask count in CMOS transistor formation'20016,218,224'Nitride disposable spacer to reduce mask count in CMOS transistor formation'20016,217,418'Polishing pad and method for polishing porous materials'20016,211,071'Optimized trench/via profile for damascene filling'20016,184,114'MOS transistor formation'20016,156,643'Method of forming a dual damascene trench and borderless via structure'20006,153,514'Self-aligned dual damascene arrangement for metal interconnection with low k dielectric constant materials and nitride middle etch stop layer'20006,121,149'Optimized trench/via profile for damascene filling'20006,117,781'Optimized trench/via profile for damascene processing'20006,117,782'Optimized trench/via profile for damascene filling'20006,107,185'Conductive material adhesion enhancement in damascene process for semiconductors'20006,103,563'Nitride disposable spacer to reduce mask count in CMOS transistor formation'20006,096,644'Self-aligned contacts to source/drain silicon electrodes utilizing polysilicon and metal silicides'20006,066,557'Method for fabricating protected copper metallization'20005,858,844'Method for construction and fabrication of submicron field-effect transistors by optimization of poly oxide process'1999Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1999–2009Patents assigned to ADVANCED MICRO DEVICES INC (66)· patent assignee history
1999–2016Based in San Jose, CA, US· patent location history
2010–2015Patents assigned to GLOBALFOUNDRIES INC (3)· patent assignee history
2016Patents assigned to CYPRESS SEMICONDUCTOR CORP (1)· patent assignee history
2016Patents assigned to LO WAI (1)· patent assignee history
2016Patents assigned to LUKANC TODD (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| ADVANCED MICRO DEVICES INC | 66 | 1999–2009 |
| GLOBALFOUNDRIES INC | 3 | 2010–2015 |
| CYPRESS SEMICONDUCTOR CORP | 1 | 2016 |
| LO WAI | 1 | 2016 |
| LUKANC TODDself | 1 | 2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 72 | 1999–2016 |