Inventor
Fu-Liang Yang
Inventor
Hsinchu, TW
Overview
Patents· 157 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices41%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1015%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
H10BElectronic memory devices10%
H10NElectric solid-state devices not otherwise provided for5%
H01LSemiconductor devices4%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests3%
G11CStatic stores2%
B24BMachines, devices, or processes for grinding or polishing1%
B28DWorking stone or stone-like materials1%
PatentTitleYear
10,861,700Diode array for connecting to phase change memory and method forming same202010,103,024Phase change memory with diodes embedded in substrate20189,960,274FinFET device for device characterization20189,905,474'CMOS device with raised source and drain regions'20189,498,784'Bio-chip and method for separating and concentrating particles using the same'20169,455,348'FinFET for device characterization'2016RE045944'Structure for a multiple-gate FET device and a method for its fabrication'20169,276,209'Phase change memory with diodes embedded in substrate'20169,190,610'Methods of forming phase change memory with various grain sizes'20159,112,144'Method of fabricating a resistive non-volatile memory device'20159,058,793'Key mechanism for a saxophone'20158,865,539'Fully depleted SOI multiple threshold voltage application'2014RE045180'Structure for a multiple-gate FET device and a method for its fabrication'20148,847,253'Programming optical device'2014RE045165'Structure for a multiple-gate FET device and a method for its fabrication'20148,835,291'Strained gate electrodes in semiconductor devices'20148,790,970'Doping of semiconductor fin devices'20148,679,728'Method for fabricating patterned layer'20148,618,524'Phase change memory with various grain sizes'20138,603,882'Method for making dual silicide and germanide semiconductors'20138,569,845'Strained silicon device'20138,564,018'Relaxed silicon germanium substrate with low defect density'20138,288,842'Method for dicing semiconductor wafers'20128,174,073'Integrated circuit structures with multiple FinFETs'20128,173,990'Memory array with a selector connected to multiple resistive cells'20128,154,003'Resistive non-volatile memory device'20128,053,839'Doping of semiconductor fin devices'20118,049,300'Inductor energy loss reduction techniques'20118,008,157'CMOS device with raised source and drain regions'20117,989,920'Phase change memory'20117,948,037'Multiple-gate transistor structure and method for fabricating'20117,943,986'Method for fabricating a body contact in a finfet structure and a device including the same'20117,923,759'Metal gate semiconductor device and manufacturing method'20117,893,420'Phase change memory with various grain sizes'20117,888,201'Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors'20117,863,674'Multiple-gate transistors formed on bulk substrates'20117,851,276'Methods and structures for planar and multiple-gate transistors formed on SOI'20107,732,310'Sidewall memory with self-aligned asymmetrical source and drain configuration'20107,728,360'Multiple-gate transistor structure'20107,704,809'Silicon-on-insulator chip with multiple crystal orientations'20107,705,424'Phase change memory'20107,701,008'Doping of semiconductor fin devices'20107,663,134'Memory array with a selector connected to multiple resistive cells'20107,659,587'Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer'20107,642,170'Phase change memory cell with roundless micro-trenches'20107,638,376'Method for forming SOI device'20097,635,632'Gate electrode for a semiconductor fin device'20097,602,006'Semiconductor flash device'20097,589,387'SONOS type two-bit FinFET flash memory cell'20097,585,711'Semiconductor-on-insulator (SOI) strained active area transistor'20097,582,947'High performance device design'20097,573,095'Memory cells with improved program/erase windows'20097,545,006'CMOS devices with graded silicide regions'20097,485,929'Semiconductor-on-insulator (SOI) strained active areas'20097,482,231'Manufacturing of memory array and periphery'20097,482,236'Structure and method for a sidewall SONOS memory device'20097,462,554'Method for forming semiconductor device with modified channel compressive stress'20087,452,778'Semiconductor nano-wire devices and methods of fabrication'20087,429,769'Recessed channel field effect transistor (FET) device'20087,423,323'Semiconductor device with raised segment'20087,405,119'Structure and method for a sidewall SONOS memory device'20087,381,649'Structure for a multiple-gate FET device and a method for its fabrication'20087,382,023'Fully depleted SOI multiple threshold voltage application'20087,368,334'Silicon-on-insulator chip with multiple crystal orientations'20087,361,541'Programming optical device'20087,357,838'Relaxed silicon germanium substrate with low defect density'20087,355,236'Non-volatile floating gate memory cells with polysilicon storage dots and fabrication methods thereof'20087,342,289'Strained silicon MOS devices'20087,319,258'Semiconductor-on-insulator chip with<100>-oriented transistors'20087,301,206'Semiconductor-on-insulator SRAM configured using partially-depleted and fully-depleted transistors'20077,300,837'FinFET transistor device on SOI and method of fabrication'20077,276,763'Structure and method for forming the gate electrode in a multiple-gate transistor'20077,268,024'Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors'20077,262,086'Contacts to semiconductor fin devices'20077,247,922'Inductor energy loss reduction techniques'20077,244,640'Method for fabricating a body contact in a Finfet structure and a device including the same'20077,238,989'Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement'20077,230,270'Self-aligned double gate device and method for forming same'20077,226,832'Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer'20077,214,991'CMOS inverters configured using multiple-gate transistors'20077,208,815'CMOS logic gate fabricated on hybrid crystal orientations and method of forming thereof'20077,202,139'MOSFET device with a strained channel'20077,187,000'High performance tunneling-biased MOSFET and a process for its manufacture'20077,183,137'Method for dicing semiconductor wafers'20077,180,134'Methods and structures for planar and multiple-gate transistors formed on SOI'20077,176,092'Gate electrode for a semiconductor fin device'20077,176,084'Self-aligned conductive spacer process for sidewall control gate of high-speed random access memory'20077,173,305'Self-aligned contact for silicon-on-insulator devices'20077,172,943'Multiple-gate transistors formed on bulk substrates'20077,170,118'Field effect transistor (FET) device having corrugated structure and method for fabrication thereof'20077,164,189'Slim spacer device and manufacturing method'20077,161,204'DRAM capacitor structure with increased electrode support for preventing process damage and exposed electrode surface for increasing capacitor area'20077,141,459'Silicon-on-insulator ULSI devices with multiple silicon film thicknesses'20067,135,372'Strained silicon device manufacturing method'20067,125,759'Semiconductor-on-insulator (SOI) strained active areas'20067,122,412'Method of fabricating a necked FINFET device'20067,105,897'Semiconductor structure and method for integrating SOI devices and bulk devices'20067,105,894'Contacts to semiconductor fin devices'20067,074,656'Doping of semiconductor fin devices'20067,053,453'Substrate contact and method of forming the same'20067,005,330'Structure and method for forming the gate electrode in a multiple-gate transistor'20066,979,867'SOI chip with mesa isolation and recess resistant regions'20056,974,730'Method for fabricating a recessed channel field effect transistor (FET) device'20056,975,006'Semiconductor device with modified channel compressive stress'20056,955,952'Strain balanced structure with a tensile strained silicon channel and a compressive strained silicon-germanium channel for CMOS performance enhancement'20056,953,972'Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer'20056,906,398'Semiconductor chip with gate dielectrics for high-performance and low-leakage applications'20056,902,962'Silicon-on-insulator chip with multiple crystal orientations'20056,878,610'Relaxed silicon germanium substrate with low defect density'20056,875,655'Method of forming DRAM capacitors with protected outside crown surface for more robust structures'20056,872,606'Semiconductor device with raised segment'20056,867,433'Semiconductor-on-insulator chip incorporating strained-channel partially-depleted, fully-depleted, and multiple-gate transistors'20056,864,519'CMOS SRAM cell configured using multiple-gate transistors'20056,864,149'SOI chip with mesa isolation and recess resistant regions'20056,855,990'Strained-channel multiple-gate transistor'20056,855,606'Semiconductor nano-rod devices'20056,844,238'Multiple-gate transistors with improved gate control'20056,835,967'Semiconductor diodes with fin structure'20046,800,516'Electrostatic discharge device protection structure'20046,784,071'Bonded SOI wafer with <100> device layer and <110> substrate for performance improvement'20046,720,619'Semiconductor-on-insulator chip incorporating partially-depleted, fully-depleted, and multiple-gate devices'20046,703,271'Complementary metal oxide semiconductor transistor technology using selective epitaxy of a strained silicon germanium layer'20046,703,187'Method of forming a self-aligned twin well structure with a single mask'20046,686,255'Amorphizing ion implant local oxidation of silicon (LOCOS) method for forming an isolation region'20046,674,130'High performance PD SOI tunneling-biased MOSFET'20046,518,105'High performance PD SOI tunneling-biased MOSFET'20036,492,216'Method of forming a transistor with a strained channel'20026,278,189'High density integrated circuits using tapered and self-aligned contacts'20016,277,709'Method of forming shallow trench isolation structure'20016,261,923'Method to solve the dishing issue in CMP planarization by using a nitride hard mask for local inverse etchback and CMP'20016,248,643'Method of fabricating a self-aligned contact'20016,239,034'Method of manufacturing inter-metal dielectric layers for semiconductor devices'20016,180,489'Formation of finely controlled shallow trench isolation for ULSI process'20016,174,815'Method for planarizing DRAM cells'20016,171,929'Shallow trench isolator via non-critical chemical mechanical polishing'20016,159,821'Methods for shallow trench isolation'20006,159,822'Self-planarized shallow trench isolation'20006,140,240'Method for eliminating CMP induced microscratches'20006,130,127'Method for making dynamic random access memory cells having cactus-shaped stacked capacitors with increased capacitance'20006,071,789'Method for simultaneously fabricating a DRAM capacitor and metal interconnections'20006,060,348'Method to fabricate isolation by combining locos and shallow trench isolation for ULSI technology'20006,057,210'Method of making a shallow trench isolation for ULSI formation via in-direct CMP process'20006,054,017'Chemical mechanical polishing pad with controlled polish rate'20006,037,216'Method for simultaneously fabricating capacitor structures, for giga-bit DRAM cells, and peripheral interconnect structures, using a dual damascene process'20006,037,259'Method for forming identifying characters on a silicon wafer'20005,994,228'Method of fabricating contact holes in high density integrated circuits using taper contact and self-aligned etching processes'19995,956,594'Method for simultaneously forming capacitor plate and metal contact structures for a high density DRAM device'19995,920,791'Method of manufacturing intermetal dielectrics for sub-half-micron semiconductor devices'19995,888,124'Apparatus for polishing and cleaning a wafer'19995,854,130'Method of forming multilevel interconnects in semiconductor devices'19985,851,874'Method of planarizing memory cells'19985,834,359'Method of forming an isolation region in a semiconductor substrate'19985,804,852'Stacked capacitor DRAM structure featuring a multiple crown shaped polysilicon lower electrode'19985,804,489'Method of manufacturing a crown shape capacitor in semiconductor memory using a single step etching'19985,792,689'Method for manufacturing double-crown capacitors self-aligned to node contacts on dynamic random access memory'19985,677,227'Method of fabricating single crown, extendible to triple crown, stacked capacitor structures, using a self-aligned capacitor node contact'19975,656,556'Method for fabricating planarized borophosphosilicate glass films having low anneal temperatures'1997Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1997–2001Patents assigned to VANGUARD INT SEMICONDUCT CORP (29)· patent assignee history
1997–2001Based in Tainan, TW· patent location history
1998Based in Chu-Nan, Miao-Li Hsien, TW· patent location history
1999–2020Based in Hsinchu, TW· patent location history
2002–2016Patents assigned to TAIWAN SEMICONDUCTOR MFG (116)· patent assignee history
2008–2013Based in Taipei, TW· patent location history
2012–2016Patents assigned to YANG FU-LIANG (17)· patent assignee history
2012–2014Patents assigned to HUANG CHIEN-CHAO (5)· patent assignee history
2015Based in Taichung, TW· patent location history
2016–2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| TAIWAN SEMICONDUCTOR MFG | 116 | 2002–2016 |
| VANGUARD INT SEMICONDUCT CORP | 29 | 1997–2001 |
| YANG FU-LIANGself | 17 | 2012–2016 |
| HUANG CHIEN-CHAO | 5 | 2012–2014 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 5 | 2016–2020 |
Locations
| Location | Patents | Span |
|---|---|---|
| Hsinchu, TW | 125 | 1999–2020 |
| Tainan, TW | 28 | 1997–2001 |
| Taipei, TW | 2 | 2008–2013 |
| Taichung, TW | 1 | 2015 |
| Chu-Nan, Miao-Li Hsien, TW | 1 | 1998 |