Inventor
Xusheng Wu
Inventor
Ballston Lake, NY, US
Overview
Patents· 87 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H01Lprimary
H01LSemiconductor devices33%
H10DInorganic electric semiconductor devices32%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1018%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1012%
G06FElectric digital data processing1%
H10BElectronic memory devices1%
G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%
Y02PClimate change mitigation technologies in the production or processing of goods1%
B82YSpecific uses or applications of nanostructures0%
G01BMeasuring length, thickness or similar linear dimensions0%
PatentTitleYear
10,879,373Structure and formation method of semiconductor device with metal gate stack202010,868,174Devices with strained isolation features202010,840,375Integrated circuits with channel-strain liner202010,818,543Source/drain contact spacers and methods of forming same202010,644,156Methods, apparatus, and system for reducing gate cut gouging and/or gate height loss in semiconductor devices202010,586,860Method of manufacturing finfet devices using narrow and wide gate cut openings in conjunction with a replacement metal gate process202010,522,679Selective shallow trench isolation (STI) fill for stress engineering in semiconductor structures201910,510,613Contact structures201910,483,369Methods of forming replacement gate structures on transistor devices201910,468,310Spacer integration scheme for FNET and PFET devices201910,461,155Epitaxial region for embedded source/drain region having uniform thickness201910,446,483Metal-insulator-metal capacitors with enlarged contact areas201910,446,683Methods, apparatus and system for forming sigma shaped source/drain lattice201910,439,026Fins with single diffusion break facet improvement using epitaxial insulator201910,388,562Composite contact etch stop layer201910,347,531Middle of the line (MOL) contact formation method and structure201910,347,740Fin structures and multi-Vt scheme based on tapered fin and method to form201910,347,729Device for improving performance through gate cut last process201910,236,218Methods, apparatus and system for forming wrap-around contact with dual silicide201910,229,999Methods of forming upper source/drain regions on a vertical transistor device201910,224,418Integrated circuit fabrication with boron etch-stop layer201910,224,330Self-aligned junction structures201910,217,846Vertical field effect transistor formation with critical dimension control201910,211,317Vertical-transport field-effect transistors with an etched-through source/drain cavity201910,204,991Transistor structures and fabrication methods thereof201910,181,468Memory cell with asymmetrical transistor, asymmetrical transistor and method of forming201910,176,995Methods, apparatus and system for gate cut process using a stress material in a finFET device201910,121,788Fin-type field effect transistors with single-diffusion breaks and method201810,068,810Multiple Fin heights with dielectric isolation201810,062,772Preventing bridge formation between replacement gate and source/drain region through STI structure201810,050,125Vertical-transport field-effect transistors with an etched-through source/drain cavity201810,032,910FinFET devices having asymmetrical epitaxially-grown source and drain regions and methods of forming the same201810,026,818Field effect transistor structure with recessed interlayer dielectric and method201810,014,409Method and structure to provide integrated long channel vertical FinFET device201810,008,576Epi facet height uniformity improvement for FDSOI technologies201810,002,827Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device20189,991,361Methods for performing a gate cut last scheme for FinFET semiconductor devices20189,972,621Fin structure in sublitho dimension for high performance CMOS application20189,972,495Low-K dielectric spacer for a gate cut20189,964,605Methods for crossed-fins FinFET device for sensing and measuring magnetic fields20189,935,104Fin-type field effect transistors with single-diffusion breaks and method20189,916,982'Dielectric preservation in a replacement gate process'20189,870,942'Method of forming mandrel and non-mandrel metal lines having variable widths'20189,865,681'Nanowire transistors having multiple threshold voltages'20189,842,913'Integrated circuit fabrication with boron etch-stop layer'20179,837,553Vertical field effect transistor20179,812,365'Methods of cutting gate structures on transistor devices'20179,793,358'Non-planar semiconductor device with multiple-head epitaxial structure on fin'20179,761,480'Methods of forming field effect transistor (FET) and non-FET circuit elements on a semiconductor-on-insulator substrate'20179,761,594'Hardmask for a halo/extension implant of a static random access memory (SRAM) layout'20179,761,491'Self-aligned deep contact for vertical FET'20179,761,691'Integrated circuits including replacement gate structures and methods for fabricating the same'20179,721,949'Method of forming super steep retrograde wells on FinFET'20179,704,971'Epi facet height uniformity improvement for FDSOI technologies'20179,679,985'Devices and methods of improving device performance through gate cut last process'20179,672,313'Method for selective re-routing of selected areas in a target layer and in adjacent interconnecting layers of an IC device'20179,647,073'Transistor structures and fabrication methods thereof'20179,607,989'Forming self-aligned NiSi placement with improved performance and yield'20179,601,392'Device characterization by time dependent charging dynamics'20179,583,625'Fin structures and multi-Vt scheme based on tapered fin and method to form'20179,576,894'Integrated circuits including organic interlayer dielectric layers and methods for fabricating the same'20179,564,375'Structures and methods for extraction of device channel width'20179,548,318'Connecting to back-plate contacts or diode junctions through a RMG electrode and resulting devices'20179,543,297'Fin-FET replacement metal gate structure and method of manufacturing the same'20179,508,794'Mixed N/P-type fin semiconductor structure with epitaxial materials having increased surface area through multiple epitaxial heads'20169,496,280'Semiconductor structure having logic region and analog region'20169,490,174'Fabricating raised fins using ancillary fin structures'20169,484,417'Methods of forming doped transition regions of transistor structures'20169,455,198'Methods of removing fins so as to form isolation structures on products that include FinFET semiconductor devices'20169,431,424'Method for creating metal gate resistor in FDSOL and resulting device'20169,418,899'Method of multi-WF for multi-Vt and thin sidewall deposition by implantation for gate-last planar CMOS and FinFET technology'20169,419,015'Method for integrating thin-film transistors on an isolation region in an integrated circuit and resulting device'20169,419,126'Integrated circuits and methods for fabricating integrated circuits with active area protection'20169,419,139'Nitride layer protection between PFET source/drain regions and dummy gate during source/drain etch'20169,379,104'Method to make gate-to-body contact to release plasma induced charging'20169,379,209'Selectively forming a protective conductive cap on a metal gate electrode'20169,343,371'Fabricating fin structures with doped middle portions'20169,337,306'Multi-phase source/drain/gate spacer-epi formation'20169,299,608'T-shaped contacts for semiconductor device'20169,275,906'Method for increasing a surface area of epitaxial structures in a mixed N/P type fin semiconductor structure by forming multiple epitaxial heads'20169,263,516'Product comprised of FinFET devices with single diffusion break isolation structures'20169,171,752'Product comprised of FinFET devices with single diffusion break isolation structures, and methods of making such a product'20159,142,640'Containment structure for epitaxial growth in non-planar semiconductor structure'20159,123,773'T-shaped single diffusion barrier with single mask approach process flow'20159,123,772'FinFET fabrication method'20159,087,720'Methods for forming FinFETs with reduced series resistance'20157,545,008'Complementary metal-oxide-semiconductor transistor structure for high density and high performance integrated circuits'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009Patents assigned to UNIV HONG KONG SCIENCE & TECHN (1)· patent assignee history
2009Based in Hong Kong, CN· patent location history
2015–2020Patents assigned to GLOBALFOUNDRIES INC (82)· patent assignee history
2015Patents assigned to GLOBALFOUNDARIES INC (1)· patent assignee history
2015–2020Based in Ballston Lake, NY, US· patent location history
2015–2019Based in Hopewell Junction, NY, US· patent location history
2020Patents assigned to TAIWAN SEMICONDUCTOR MFG CO LTD (4)· patent assignee history
2020Based in Hsinchu, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| GLOBALFOUNDRIES INC | 82 | 2015–2020 |
| TAIWAN SEMICONDUCTOR MFG CO LTD | 4 | 2020 |
| GLOBALFOUNDARIES INC | 1 | 2015 |
| UNIV HONG KONG SCIENCE & TECHN | 1 | 2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Ballston Lake, New York, US | 78 | 2015–2020 |
| Hsinchu, TW | 4 | 2020 |
| Hopewell Junction, New York, US | 4 | 2015–2019 |
| Hong Kong, CN | 1 | 2009 |