LexDanaLexDanabeta
Inventor

Jeffrey Orion Pritchard

Inventor
Santa Cruz, CA, US

Overview

58→
Patents
1999–2018
Patent span
Physics
Primary field (CPC G)

Patents· 58 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

G06Fprimary
G06FElectric digital data processing51%
B61CLocomotives12%
Y02TClimate change mitigation technologies related to transportation12%
H04NPictorial communication, e.g. television5%
B60LPropulsion of electrically-propelled vehicles4%
B61LGuiding railway traffic4%
G01RMeasuring electric variables2%
G06VImage or video recognition or understanding2%
B64CAeroplanes1%
B64UUnmanned aerial vehicles [uav]1%
PatentTitleYear
9,989,965Object detection and analysis via unmanned aerial vehicle20189,821,819'Auxiliary power unit assembly and method of use'20179,630,633'Apparatus and method for controlling a locomotive consist'20179,403,539'Apparatus and method for controlling a locomotive consist'20169,329,847'High-level language code sequence optimization for implementing programmable chip designs'20169,321,467'Fuel tank assembly and method of use'20169,145,149'Auxiliary power unit assembly and method of use'20159,114,812'Apparatus and method for controlling a locomotive consist having a locomotive and auxiliary power unit'20159,014,884'Apparatus and method for controlling a locomotive consist'20158,977,531'Apparatus and methods for importing hardware design and generating circuit interfaces'20158,880,248'Auxiliary power unit assembly and method of use'20148,855,839'Fuel tank assembly and method of use'20148,706,931'Tool selection and implementation of port adapters'20148,606,558'Apparatus and methods for importing hardware design and generating circuit interfaces'20138,600,590'Auxiliary power unit assembly and method of use'20138,578,356'High-level language code sequence optimization for implementing programmable chip designs'20138,543,949'Allocating hardware resources for high-level language code sequences'20138,291,396'Scheduling optimization of aliased pointers for implementation on programmable chips'20128,286,025'Selection of port adapters for clock crossing boundaries'20128,234,101'Apparatus and methods for importing hardware design and generating circuit interfaces'20128,219,785'Adapter allowing unaligned access to memory'20128,191,035'Tool with graphical interconnect matrix'20128,161,444'Allocating hardware resources for high-level language code sequences'20128,156,455'Methods and apparatus for implementing parameterizable processors and peripherals'20128,132,132'Methods and apparatus for implementing parameterizable processors and peripherals'20128,082,378'Master and slave side arbitrators associated with programmable chip system components'20118,037,434'Methods and apparatus for implementing parameterizable processors and peripherals'20117,890,317'Apparatus and methods for importing hardware design and generating circuit interfaces'20117,873,953'High-level language code sequence optimization for implementing programmable chip designs'20117,809,861'System memory map decoder logic'20107,802,221'Design tool with graphical interconnect matrix'20107,779,286'Design tool clock domain crossing management'20107,769,934'Master and slave side arbitrators associated with programmable chip system components'20107,769,929'Design tool selection and implementation of port adapters'20107,730,435'Automatic test component generation and inclusion into simulation testbench'20107,675,931'Methods and apparatus for controlling multiple master/slave connections'20107,676,784'Methods and apparatus for implementing parameterizable processors and peripherals'20107,636,817'Methods and apparatus for allowing simultaneous memory accesses in a programmable chip system'20097,533,362'Allocating hardware resources for high-level language code sequences'20097,493,584'Methods and apparatus for selective comment assertion'20097,409,670'Scheduling logic on a programmable device implemented using a high-level language'20087,395,360'Programmable chip bus arbitration logic'20087,370,311'Generating components on a programmable device using a high-level language'20087,353,484'Methods and apparatus for variable latency support'20087,346,863'Hardware acceleration of high-level language code sequences on programmable devices'20087,331,022'Method and apparatus for automating pin assignments'20087,302,667'Methods and apparatus for generating programmable device layout information'20077,272,546'Apparatus and methods for importing hardware design and generating circuit interfaces'20077,246,185'Master and slave side arbitrators associated with programmable chip system components'20077,225,416'Methods and apparatus for automatic test component generation and inclusion into simulation testbench'20077,149,827'Methods and apparatus for tristate line sharing'20067,036,107'Methods and apparatus for selective comment assertion'20066,976,239'Methods and apparatus for implementing parameterizable processors and peripherals'20056,857,035'Methods and apparatus for bus mastering and arbitration'20056,853,404'Electronic view camera for tripod mounting'20056,636,261'Driven capacitor storage pixel sensor and array'20036,054,704'Driven capacitor storage pixel sensor and array'20005,861,583'Object position detector'1999

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1999–2018Based in San Francisco, CA, US· patent location history
2005–2016Patents assigned to ALTERA CORP (42)· patent assignee history
2005–2016Based in Santa Cruz, CA, US· patent location history
2011–2014Patents assigned to PRITCHARD JEFFREY ORION (11)· patent assignee history
2011–2013Patents assigned to ALLEN TIM (5)· patent assignee history
2013–2016Patents assigned to BRIGHT ENERGY STORAGE TECHNOLOGIES LLP (7)· patent assignee history
2013–2017Based in Oakland, CA, US· patent location history
2015Based in San Jose, CA, US· patent location history
2016–2017Patents assigned to BRIGHT ENERGY STORAGE TECH LLP (3)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees
AssigneePatentsSpan
ALTERA CORP422005–2016
PRITCHARD JEFFREY ORIONself112011–2014
BRIGHT ENERGY STORAGE TECHNOLOGIES LLP72013–2016
ALLEN TIM52011–2013
BRIGHT ENERGY STORAGE TECH LLP32016–2017
Locations
LocationPatentsSpan
Santa Cruz, California, US422005–2016
Oakland, California, US102013–2017
San Francisco, California, US51999–2018
San Jose, California, US12015