Inventor
ROBERT MARK ENGLEKIRK
Inventor
US
Overview
Patents· 33 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H03Fprimary
H03FAmplifiers14%
H03KPulse technique13%
G05FSystems for regulating electric or magnetic variables10%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h108%
H03MCoding7%
H01LSemiconductor devices6%
H10DInorganic electric semiconductor devices6%
G06FElectric digital data processing5%
H01HElectric switches5%
G01RMeasuring electric variables4%
PatentTitleYear
12,580,566Output buffer for a swappable single conductor interface202612,517,852Pin determination for single-conductor interface systems and methods202612,431,890Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals202512,399,209Current measurement for defect detection202512,322,713Transient stabilized SOI FETs202512,313,703Low-voltage fuse read circuit202512,298,798Controllable temperature coefficient bias circuit202512,255,587Gate drivers for stacked transistor amplifiers202512,255,588Cascode amplifier bias circuits202512,242,293Low-noise high efficiency bias generation circuits and method202512,237,835PIN determination for single-conductor interface202512,191,833Power amplifier self-heating compensation circuit202512,166,477Tuning capacitance to enhance fet stack voltage withstand202412,032,040Low-voltage fuse read circuit202412,009,744Charge pump with fractional negative voltage output202412,007,803Controllable temperature coefficient bias circuit202411,955,932Cascode amplifier bias circuits202411,948,897Transient stabilized SOI FETs202411,894,840Output buffer for a swappable single conductor interface202411,888,468Tuning capacitance to enhance FET stack voltage withstand202411,742,802Gate drivers for stacked transistor amplifiers202311,720,136Controllable temperature coefficient bias circuit202311,671,091Devices and methods for improving voltage handling and/or bi-directionality of stacks of elements when connected between terminals202311,664,769Cascode amplifier bias circuits202311,662,755Low-noise high efficiency bias generation circuits and method202311,641,159Fast detection and discharge for charge pump controller202311,614,759Leakage compensation circuit202311,507,125Controllable temperature coefficient bias circuit202211,451,205Power amplifier self-heating compensation circuit202211,374,540Cascode amplifier bias circuits202211,251,140Transient stabilized SOI FETs202211,188,106Low-noise high efficiency bias generation circuits and method202111,190,139Gate drivers for stacked transistor amplifiers2021Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2021–2025Patents assigned to PSEMI CORP (28)· patent assignee history
2021–2026Based in US· patent location history
2024–2026Patents assigned to MURATA MANUFACTURING CO (5)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| PSEMI CORP | 28 | 2021–2025 |
| MURATA MANUFACTURING CO | 5 | 2024–2026 |
Locations
| Location | Patents | Span |
|---|---|---|
| US | 33 | 2021–2026 |