Inventor

Kirk D. Prall

Inventor

Boise, ID, US

Overview

1993–2021

Patent span

Electricity

Primary field (CPC H)

Patents· 215 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H10Dprimary

H10DInorganic electric semiconductor devices24%

H10BElectronic memory devices19%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1014%

G11CStatic stores13%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h109%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests6%

H01LSemiconductor devices5%

H10NElectric solid-state devices not otherwise provided for3%

B82YSpecific uses or applications of nanostructures1%

C23CCoating metallic material1%

PatentTitleYear

11,068,166Hybrid memory device using different types of capacitors and operating method thereof2021 11,004,510Cross-point memory compensation2021 10,978,128Memory cell imprint avoidance2021 10,943,986Transistors, memory cells and semiconductor constructions comprising ferroelectric gate dielectric2021 10,943,915Integrated memory having the body region comprising a different semiconductor composition than the source/drain region2021 10,741,567Memory cells2020 10,727,336Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors2020 10,679,696Cross-point memory compensation2020 10,629,732Elevationally-extending transistors, devices comprising elevationally-extending transistors, and methods of forming a device comprising elevationally-extending transistors2020 10,475,500Memory cell imprint avoidance2019 10,282,108Hybrid memory device using different types of capacitors2019 10,217,753Memory cells2019 10,083,732Memory cell imprint avoidance2018 10,084,084Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors2018 9,887,204'Memory cells'2018 9,882,016'Transistors, memory cells and semiconductor constructions'2018 9,761,715'Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors'2017 9,721,639'Memory cell imprint avoidance'2017 9,679,642'Cross-point memory compensation'2017 9,673,203'Memory cells'2017 9,590,066'Transistors, memory cells and semiconductor constructions'2017 9,548,335'Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines'2017 9,378,818'Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines'2016 9,343,674'Cross-point memory utilizing Ru/Si diode'2016 9,305,929'Memory cells'2016 9,287,275'Semiconductor constructions'2016 9,263,577'Ferroelectric field effect transistors, pluralities of ferroelectric field effect transistors arrayed in row lines and column lines, and methods of forming a plurality of ferroelectric field effect transistors'2016 9,263,672'Transistors, memory cells and semiconductor constructions'2016 9,142,767'Resistive memory cell including integrated select device and storage element'2015 9,099,314'Pitch multiplication spacers and methods of forming the same'2015 9,058,857'Cross-point memory compensation'2015 8,976,566'Electronic devices, memory devices and memory arrays'2015 8,841,645'Multi-level memory cell'2014 8,803,125'Cross-point memory utilizing Ru/Si diode'2014 8,796,751'Transistors, memory cells and semiconductor constructions'2014 8,729,621'Memory devices comprising word line structures, at least one select gate structure, and a plurality of doped regions'2014 8,681,529'Apparatuses and operation methods associated with resistive memory cell arrays with separate select lines'2014 8,647,949'Structure and method of fabricating a transistor having a trench gate'2014 8,580,645'Memory devices and methods of forming memory devices'2013 8,441,056'NROM memory cell, memory array, related devices and methods'2013 8,415,223'Memory devices and methods of forming memory devices'2013 8,395,140'Cross-point memory utilizing Ru/Si diode'2013 8,369,150'Relaxed metal pitch memory architectures'2013 8,351,242'Electronic devices, memory devices and memory arrays'2013 8,330,139'Multi-level memory cell'2012 8,268,692'Non-volatile memory cell devices and methods'2012 8,129,781'Method of forming memory devices by performing halogen ion implantation and diffusion processes'2012 8,102,714'Programming methods for multi-level memory devices'2012 8,063,436'Memory cells configured to allow for erasure by enhanced F-N tunneling of holes from a control gate to a charge trapping material'2011 7,956,402'Double-doped polysilicon floating gate'2011 7,955,935'Non-volatile memory cell devices and methods'2011 7,911,837'Multi-state memory cell with asymmetric charge trapping'2011 7,897,470'Non-volatile memory cell device and methods'2011 7,879,665'Structure and method of fabricating a transistor having a trench gate'2011 7,881,113'Relaxed metal pitch memory architectures'2011 7,824,994'Method of forming memory devices by performing halogen ion implantation and diffusion processes'2010 7,776,744'Pitch multiplication spacers and methods of forming the same'2010 7,750,389'NROM memory cell, memory array, related devices and methods'2010 7,749,848'Band-engineered multi-gated non-volatile memory device with enhanced attributes'2010 7,745,283'Method of fabricating memory transistor'2010 7,696,557'Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation'2010 7,684,249'Programming methods for multi-level memory devices'2010 7,651,911'Memory transistor and methods'2010 7,616,482'Multi-state memory cell with asymmetric charge trapping'2009 7,588,982'Methods of forming semiconductor constructions and flash memory cells'2009 7,577,027'Multi-state memory cell with asymmetric charge trapping'2009 7,569,468'Method for forming a floating gate memory with polysilicon local interconnects'2009 7,560,769'Non-volatile memory cell device and methods'2009 7,541,242'NROM memory cell, memory array, related devices and methods'2009 7,535,048'NROM memory cell, memory array, related devices and methods'2009 7,517,749'Method for forming an array with polysilicon local interconnects'2009 7,485,528'Method of forming memory devices by performing halogen ion implantation and diffusion processes'2009 7,417,280'Method and apparatus for a flash memory device comprising a source local interconnect'2008 7,338,856'Double-doped polysilicon floating gate'2008 7,332,419'Structure and method of fabricating a transistor having a trench gate'2008 7,301,804'NROM memory cell, memory array, related devices and methods'2007 7,279,740'Band-engineered multi-gated non-volatile memory device with enhanced attributes'2007 7,279,710'Structure and method of fabricating a transistor having a trench gate'2007 7,269,072'NROM memory cell, memory array, related devices and methods'2007 7,269,071'NROM memory cell, memory array, related devices and methods'2007 7,262,503'Semiconductor constructions'2007 7,220,634'NROM memory cell, memory array, related devices and methods'2007 7,199,422'Contactless uniform-tunneling separate P-well (CUSP) non-volatile memory array architecture, fabrication and operation'2007 7,157,305'Forming multi-layer memory arrays'2007 7,115,509'Method for forming polysilicon local interconnects'2006 7,112,815'Multi-layer memory arrays'2006 7,112,542'Methods of forming materials between conductive electrical components, and insulating materials'2006 7,085,164'Programming methods for multi-level flash EEPROMs'2006 7,072,217'Multi-state memory cell with asymmetric charge trapping'2006 7,053,444'Method and apparatus for a flash memory device comprising a source local interconnect'2006 7,035,145'Programming methods for multi-level flash EEPROMs'2006 6,998,314'Fabricating a 2F2 memory device with a horizontal floating gate'2006 6,984,547'Contactless uniform-tunneling separate p-well (cusp) non-volatile memory array architecture, fabrication and operation'2006 6,949,795'Structure and method of fabricating a transistor having a trench gate'2005 6,930,350'Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation'2005 6,927,445'Method to form a corrugated structure for enhanced capacitance'2005 6,924,186'Method of forming a memory device and semiconductor device'2005 6,882,003'Method and apparatus for a flash memory device comprising a source local interconnect'2005 6,858,526'Methods of forming materials between conductive electrical components, and insulating materials'2005 6,845,039'Programming methods for multi-level flash EEPROMS'2005 6,835,619'Method of forming a memory transistor comprising a Schottky contact'2004 6,812,512'Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture'2004 6,812,160'Methods of forming materials between conductive electrical components, and insulating materials'2004 6,791,140'Memory transistor structure'2004 6,777,732'Random access memory'2004 6,759,707'2F2 memory device system'2004 6,750,494'Semiconductor buried contact with a removable spacer'2004 6,750,502'Technique to quench electrical defects in aluminum oxide film'2004 6,737,320'Double-doped polysilicon floating gate'2004 6,686,288'Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture'2004 6,686,238'Method of forming a semiconductor memory device'2004 6,667,554'Expanded implantation of contact holes'2003 6,660,611'Method to form a corrugated structure for enhanced capacitance with plurality of boro-phospho silicate glass including germanium'2003 6,649,453'Contactless uniform-tunneling separate p-well (CUSP) non-volatile memory array architecture, fabrication and operation'2003 6,632,727'Expanded implantation of contact holes'2003 6,624,024'Method and apparatus for a flash memory device comprising a source local interconnect'2003 6,597,054'Reduced pitch laser redundancy fuse bank structure'2003 6,586,304'SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS, METHOD OF FORMING A SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, AND METHOD OF FORMING MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS'2003 6,522,584'Programming methods for multi-level flash EEPROMs'2003 6,514,842'Low resistance gate flash memory'2003 6,501,179'Constructions comprising insulative materials'2002 6,489,665'Lateral bipolar transistor'2002 6,472,756'Method of forming titanium silicide and titanium by chemical vapor deposition and resulting apparatus'2002 6,469,389'Contact plug'2002 6,459,610'SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS, METHOD OF FORMING A SEMICONDUCTOR-ON-INSULATOR TRANSISTOR, AND METHOD OF FORMING MEMORY CIRCUITRY EMPLOYING SEMICONDUCTOR-ON-INSULATOR TRANSISTORS'2002 6,448,656'System including a memory device having a semiconductor connection with a top surface having an enlarged recess'2002 6,442,066'Flash memory with overerase protection'2002 6,429,526'Method for forming a semiconductor connection with a top surface having an enlarged recess'2002 6,426,287'Method for forming a semiconductor connection with a top surface having an enlarged recess'2002 6,406,959'Method of forming FLASH memory, method of forming FLASH memory and SRAM circuitry, and etching methods'2002 6,406,998'Formation of silicided contact by ion implantation'2002 6,404,669'Reduced leakage DRAM storage unit'2002 6,404,008'Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors'2002 6,346,455'Method to form a corrugated structure for enhanced capacitance'2002 6,337,244'Method of forming flash memory'2002 6,333,556'Insulating materials'2001 6,326,250'Semiconductor processing method of fabricating field effect transistors'2001 6,313,046'Method of forming materials between conductive electrical components, and insulating materials'2001 6,303,492'Expanded implantation of contact holes'2001 6,288,419'Low resistance gate flash memory'2001 6,282,126'Flash memory with overerase protection'2001 6,277,731'Method for forming a semiconductor connection with a top surface having an enlarged recess'2001 6,274,897'Semiconductor structure having interconnects on a projecting region and substrate'2001 6,274,423'Etch process for aligning a capacitor structure and an adjacent contact corridor'2001 6,255,209'Methods of forming a contact having titanium formed by chemical vapor deposition'2001 6,255,216'Methods of forming a contact having titanium silicide and titanium formed by chemical vapor deposition'2001 6,255,693'Ion implantation with programmable energy, angle, and beam current'2001 6,229,148'Ion implantation with programmable energy, angle, and beam current'2001 6,211,007'Process for enhancing refresh in dynamic random access memory devices'2001 6,208,033'Apparatus having titanium silicide and titanium formed by chemical vapor deposition'2001 6,207,571'Self-aligned contact formation for semiconductor devices'2001 6,181,594'Reduced leakage DRAM storage unit'2001 6,171,943'Methods of forming a contact having titanium silicide formed by chemical vapor deposition'2001 6,166,426'Lateral bipolar transistors and systems using such'2000 6,160,277'Field effect transistor assemblies and transistor gate block stacks'2000 6,157,565'Reduced leakage DRAM storage unit'2000 6,157,566'Reduced leakage DRAM storage unit'2000 6,150,204'Semiconductor processing method of fabricating field effect transistors'2000 6,130,137'Method of forming a resistor and integrated circuitry having a resistor construction'2000 6,127,236'Method of forming a lateral bipolar transistor'2000 6,083,799'Semiconductor processing method of forming a field effect transistor'2000 6,080,672'Self-aligned contact formation for semiconductor devices'2000 6,080,675'Method for cleaning waste matter from the backside of a semiconductor wafer substrate'2000 6,067,680'Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening'2000 6,066,559'Method for forming a semiconductor connection with a top surface having an enlarged recess'2000 6,060,783'Self-aligned contact plugs'2000 6,057,200'Method of making a field effect transistor having an elevated source and an elevated drain'2000 6,043,151'Method for forming a semiconductor connection with a top surface having an enlarged recess'2000 6,010,953'Method for forming a semiconductor buried contact with a removable spacer'2000 6,005,801'Reduced leakage DRAM storage unit'1999 5,998,844'Semiconductor constructions comprising electrically conductive plugs having monocrystalline and polycrystalline silicon'1999 5,994,220'Method for forming a semiconductor connection with a top surface having an enlarged recess'1999 5,990,021'Integrated circuit having self-aligned CVD-tungsten/titanium contact plugs strapped with metal interconnect and method of manufacture'1999 5,986,347'Processing methods of forming contact openings and integrated circuitry'1999 5,976,976'Method of forming titanium silicide and titanium by chemical vapor deposition'1999 5,976,985'Processing methods of forming contact openings and integrated circuitry'1999 5,965,923'Lateral bipolar transistor and apparatus using same'1999 5,958,796'Method for cleaning waste matter from the backside of a semiconductor wafer substrate'1999 5,945,726'Lateral bipolar transistor'1999 5,945,348'Method for reducing the heights of interconnects on a projecting region with a smaller reduction in the heights of other interconnects'1999 5,945,698'Field effect transistor assemblies and transistor gate block stacks'1999 5,940,712'Method of forming a resistor and integrated circuitry having a resistor construction'1999 5,929,476'Semiconductor-on-insulator transistor and memory circuitry employing semiconductor-on-insulator transistors'1999 5,923,078'Method of forming a resistor and integrated circuitry having a resistor construction'1999 5,905,295'Reduced pitch laser redundancy fuse bank structure'1999 5,896,309'Semiconductor-on-insulator transistor, memory circuitry employing semiconductor-on-insulator transistors, method of forming a semiconductor-on-insulator transistor, and method of forming memory circuitry employing semiconductor-on-insulator transistors'1999 5,892,285'Semiconductor connection with a top surface having an enlarged recess'1999 5,866,453'Etch process for aligning a capacitor structure and an adjacent contact corridor'1999 5,858,865'Method of forming contact plugs'1999 5,849,615'Semiconductor processing method of fabricating field effect transistors'1998 5,831,334'Field effect transistors comprising electrically conductive plugs having monocrystalline and polycrystalline silicon'1998 5,821,150'Method of forming a resistor and integrated circuitry having a resistor construction'1998 5,804,506'Acceleration of etch selectivity for self-aligned contact'1998 5,780,920'Method of forming a resistor and integrated circuitry having a resistor construction'1998 5,759,905'Semiconductor processing method of forming a conductively doped semiconductive material plug within a contact opening'1998 RE035810'Plug-based floating gate memory'1998 5,747,869'Reduced pitch laser redundancy fuse bank structure'1998 5,733,709'Semiconductor processing method of forming a field effect transistor'1998 5,728,596'Method for forming a semiconductor buried contact with a removable spacer'1998 5,716,862'High performance PMOSFET using split-polysilicon CMOS process incorporating advanced stacked capacitior cells for fabricating multi-megabit DRAMS'1998 5,716,873'Method for cleaning waste matter from the backside of a semiconductor wafer substrate'1998 5,677,573'Field effect transistor'1997 5,668,037'Method of forming a resistor and integrated circuitry having a resistor construction'1997 5,650,349'Process for enhancing refresh in dynamic random access memory device'1997 5,637,518'Method of making a field effect transistor having an elevated source and an elevated drain'1997 5,636,172'Reduced pitch laser redundancy fuse bank structure'1997 5,605,864'Method for forming a semiconductor buried contact with a removable spacer'1997 5,597,746'Method of forming field effect transistors relative to a semiconductor substrate and field effect transistors produced according to the method'1997 5,488,011'Method of forming contact areas between vertical conductors'1996 5,424,569'Array of non-volatile sonos memory cells'1995 5,387,534'Method of forming an array of non-volatile sonos memory cells and array of non-violatile sonos memory cells'1995 5,345,104'Flash memory cell having antimony drain for reduced drain voltage during programming'1994 5,341,016'Low resistance device element and interconnection structure'1994 5,281,548'Plug-based floating gate memory'1994 5,185,275'Snap-back preventing method for high voltage MOSFET'1993

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1993–2021Patents assigned to MICRON TECHNOLOGY INC (206)· patent assignee history

1993–2021Based in Boise, ID, US· patent location history

2010–2014Patents assigned to ROUND ROCK RES LLC (4)· patent assignee history

2011–2016Patents assigned to PRALL KIRK D (16)· patent assignee history

2012–2016Patents assigned to SANDHU GURTEJ S (3)· patent assignee history

2012–2013Patents assigned to ARITOME SEIICHI (2)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
MICRON TECHNOLOGY INC	206	1993–2021
PRALL KIRK Dself	16	2011–2016
ROUND ROCK RES LLC	4	2010–2014
SANDHU GURTEJ S	3	2012–2016
ARITOME SEIICHI	2	2012–2013

Locations

Location	Patents	Span
Boise, ID, US	215	1993–2021