Inventor

Irving Memis

Inventor

Vestal, NY, US

Overview

35→

Patents

1977–2012

Patent span

Electricity

Primary field (CPC H)

Patents· 35 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H05Kprimary

H05KPrinted circuits35%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1031%

Y10TTechnical subjects covered by former us classification16%

B32BLayered products, i.e. products built-up of strata of flat or non-flat, e.g. cellular or honeycomb, form5%

Y02PClimate change mitigation technologies in the production or processing of goods5%

Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests4%

B05DProcesses for applying fluent materials to surfaces, in general1%

C09DCoating compositions, e.g. paints, varnishes or lacquers1%

C09JAdhesives1%

C23CCoating metallic material1%

PatentTitleYear

8,144,480'Multi-layer embedded capacitance and resistance substrate core'2012 7,886,435'High performance chip carrier substrate'2011 7,863,526'High performance chip carrier substrate'2011 7,791,897'Multi-layer embedded capacitance and resistance substrate core'2010 7,622,384'Method of making multi-chip electronic package with reduced line skew'2009 7,589,283'Method of making circuitized substrate with improved impedance control circuitry, electrical assembly and information handling system'2009 7,470,990'Low moisture absorptive circuitized substrate with reduced thermal expansion, method of making same, electrical assembly utilizing same, and information handling system utilizing same'2008 7,454,833'High performance chip carrier substrate'2008 7,416,972'Method of making same low moisture absorptive circuitized substrave with reduced thermal expansion'2008 7,332,818'Multi-chip electronic package with reduced line skew and circuitized substrate for use therein'2008 7,294,791'Circuitized substrate with improved impedance control circuitry, method of making same, electrical assembly and information handling system utilizing same'2007 7,279,798'High wireability microvia substrate'2007 7,214,886'High performance chip carrier substrate'2007 7,145,221'Low moisture absorptive circuitized substrate, method of making same, electrical assembly utilizing same, and information handling system utilizing same'2006 7,119,003'Extension of fatigue life for C4 solder ball to chip connection'2006 7,067,916'Extension of fatigue life for C4 solder ball to chip connection'2006 6,965,170'High wireability microvia substrate'2005 6,919,635'High density microvia substrate with high wireability'2005 6,664,485'Full additive process with filled plated through holes'2003 6,650,016'Selective C4 connection in IC packaging'2003 6,418,616'Full additive process with filled plated through holes'2002 6,391,210'Process for manufacturing a multi-layer circuit board'2002 6,290,860'Process for design and manufacture of fine line circuits on planarized thin film dielectrics and circuits manufactured thereby'2001 6,251,707'Attaching heat sinks directly to flip chips and ceramic chip carriers'2001 6,195,883'Full additive process with filled plated through holes'2001 6,162,997'Circuit board with primary and secondary through holes'2000 6,069,023'Attaching heat sinks directly to flip chips and ceramic chip carriers'2000 5,965,944'Printed circuit boards for mounting a semiconductor integrated circuit die'1999 5,847,929'Attaching heat sinks directly to flip chips and ceramic chip carriers'1998 5,532,024'Method for improving the adhesion of polymeric adhesives to nickel surfaces'1996 5,414,928'Method of making an electronic package assembly with protective encapsulant material'1995 5,189,261'Electrical and/or thermal interconnections and methods for obtaining such'1993 4,971,894'Method and structure for preventing wet etchant penetration at the interface between a resist mask and an underlying metal layer'1990 4,233,620'Sealing of integrated circuit modules'1980 4,048,356'Hermetic topsealant coating and process for its formation'1977

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

1977–2011Patents assigned to IBM (26)· patent assignee history

1977–2012Based in Vestal, NY, US· patent location history

2006–2012Patents assigned to ENDICOTT INTERCONNECT TECH INC (9)· patent assignee history

2012Patents assigned to DAS RABINDRA N (1)· patent assignee history

2012Patents assigned to LAUFFER JOHN M (1)· patent assignee history

2012Patents assigned to MEMIS IRVING (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	26	1977–2011
ENDICOTT INTERCONNECT TECH INC	9	2006–2012
DAS RABINDRA N	1	2012
LAUFFER JOHN M	1	2012
MEMIS IRVINGself	1	2012

Locations

Location	Patents	Span
Vestal, New York, US	35	1977–2012