Inventor
Jay B. Patel
Inventor
Los Gatos, CA, US
Overview
Patents· 21 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing38%
H04LTransmission of digital information, e.g. telegraphic communication26%
G11CStatic stores15%
H03MCoding5%
H04JMultiplex communication5%
G06KGraphical data reading3%
G06VImage or video recognition or understanding3%
H03KPulse technique3%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use3%
PatentTitleYear
11,010,605Multi-model detection of objects202110,324,642Peripheral component interconnect express (PCIe) solid state drive (SSD) accelerator201910,114,558Integrated main memory and coprocessor with low latency20189,971,567Method and apparatus for randomizer20189,921,755'Integrated main memory and coprocessor with low latency'20189,667,546'Programmable partitionable counter'20179,529,569'Method and apparatus for randomizer'20169,496,009'Memory with bank-conflict-resolution (BCR) module including cache'20169,361,196'Memory device with background built-in self-repair using background built-in self-testing'20169,354,823'Memory system including variable write burst and broadcast command scheduling'20169,118,611'Data synchronization for circuit resources without using a resource buffer'20159,037,928'Memory device with background built-in self-testing and background built-in self-repair'20158,832,336'Reducing latency in serializer-deserializer links'20148,824,468'System and method for parsing frames'20148,635,417'Memory system including variable write command scheduling'20148,527,676'Reducing latency in serializer-deserializer links'20138,473,695'Memory system including variable write command scheduling'20138,370,725'Communication interface and protocol'20138,050,262'System and method for parsing frames'20117,773,595'System and method for parsing frames'20107,557,605'Heterogeneous configurable integrated circuit'2009Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2009–2018Based in Los Gatos, CA, US· patent location history
2010–2014Patents assigned to AGATE LOGIC INC (3)· patent assignee history
2013–2018Patents assigned to MOSYS INC (15)· patent assignee history
2013–2014Patents assigned to PATEL JAY B (6)· patent assignee history
2013–2014Patents assigned to MORRISON MICHAEL J (5)· patent assignee history
2013–2014Patents assigned to FEROLITO PHILIP A (3)· patent assignee history
2019Based in San Jose, CA, US· patent location history
2021Based in Sunnyvale, CA, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| MOSYS INC | 15 | 2013–2018 |
| PATEL JAY Bself | 6 | 2013–2014 |
| MORRISON MICHAEL J | 5 | 2013–2014 |
| AGATE LOGIC INC | 3 | 2010–2014 |
| FEROLITO PHILIP A | 3 | 2013–2014 |
Locations
| Location | Patents | Span |
|---|---|---|
| Los Gatos, California, US | 19 | 2009–2018 |
| Sunnyvale, California, US | 1 | 2021 |
| San Jose, California, US | 1 | 2019 |