Inventor
JoHyun Bae
Inventor
Seoul, KR
Overview
Patents· 23 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1085%
H01LSemiconductor devices15%
PatentTitleYear
9,349,666'Integrated circuit packaging system with package stacking'20169,330,945'Integrated circuit package system with multi-chip module'20169,093,392'Integrated circuit packaging system with vertical interconnection and method of manufacture thereof'20159,093,391'Integrated circuit packaging system with fan-in package and method of manufacture thereof'20158,772,916'Integrated circuit package system employing mold flash prevention technology'20148,698,297'Integrated circuit packaging system with stack device'20148,699,232'Integrated circuit packaging system with interposer and method of manufacture thereof'20148,674,516'Integrated circuit packaging system with vertical interconnects and method of manufacture thereof'20148,643,181'Integrated circuit packaging system with encapsulation and method of manufacture thereof'20148,569,869'Integrated circuit packaging system with encapsulation and method of manufacture thereof'20138,501,535'Integrated circuit package system with dual side connection and method for manufacturing thereof'20138,497,575'Semiconductor packaging system with an aligned interconnect and method of manufacture thereof'20138,461,680'Integrated circuit packaging system with rounded interconnect'20138,304,900'Integrated circuit packaging system with stacked lead and method of manufacture thereof'20128,252,615'Integrated circuit package system employing mold flash prevention technology'20128,232,141'Integrated circuit packaging system with conductive pillars and method of manufacture thereof'20128,129,832'Mountable integrated circuit package system with substrate having a conductor-free recess'20128,039,275'Integrated circuit packaging system with rounded interconnect and method of manufacture thereof'20117,923,304'Integrated circuit packaging system with conductive pillars and method of manufacture thereof'20117,884,457'Integrated circuit package system with dual side connection'20117,800,212'Mountable integrated circuit package system with stacking interposer'20107,710,735'Multichip package system'20107,687,897'Mountable integrated circuit package-in-package system with adhesive spacing structures'2010Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2010–2016Patents assigned to STATS CHIPPAC LTD (23)· patent assignee history
2010–2016Based in Seoul, KR· patent location history
2012–2016Patents assigned to BAE JOHYUN (17)· patent assignee history
2012–2016Patents assigned to CHOI DAESIK (5)· patent assignee history
2012–2016Patents assigned to YOON IN SANG (5)· patent assignee history
2013–2016Patents assigned to AHN SEUNGYUN (4)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| STATS CHIPPAC LTD | 23 | 2010–2016 |
| BAE JOHYUNself | 17 | 2012–2016 |
| CHOI DAESIK | 5 | 2012–2016 |
| YOON IN SANG | 5 | 2012–2016 |
| AHN SEUNGYUN | 4 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| Seoul, KR | 23 | 2010–2016 |