Inventor
Yoshihiko Nagayasu
Inventor
Nagano, JP
Overview
Patents· 5 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Dprimary
H10DInorganic electric semiconductor devices63%
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1025%
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1013%
PatentTitleYear
7,510,975'Method for manufacturing a semiconductor device having trenches defined in the substrate surface'20096,087,688'Field effect transistor'20005,972,768'Method of manufacturing semiconductor device having low contact resistance'19995,591,657'Semiconductor apparatus manufacturing method employing gate side wall self-aligning for masking'19975,340,756'Method for producing self-aligned LDD CMOS, DMOS with deeper source/drain and P-base regions and, bipolar devices on a common substrate'1994Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1994–2000Patents assigned to FUJI ELECTRIC CO LTD (4)· patent assignee history
1994Based in Kawasaki, JP· patent location history
1997–2009Based in Nagano, JP· patent location history
2009Patents assigned to FUJI ELECTRIC HOLDINGS (1)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| FUJI ELECTRIC CO LTD | 4 | 1994–2000 |
| FUJI ELECTRIC HOLDINGS | 1 | 2009 |
Locations
| Location | Patents | Span |
|---|---|---|
| Nagano, JP | 4 | 1997–2009 |
| Kawasaki, JP | 1 | 1994 |