Inventor
John Shen
Inventor
San Jose, CA, US
Overview
Patents· 81 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing88%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use4%
G06TImage data processing or generation, in general3%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests2%
G01RMeasuring electric variables1%
Y02BClimate change mitigation technologies related to buildings, e.g. housing, house appliances or related end-user applications1%
PatentTitleYear
10,877,910Programmable event driven yield mechanism which may activate other threads202010,635,438Method and system to provide user-level multithreading202010,628,153Method and system to provide user-level multithreading202010,613,858Method and system to provide user-level multithreading202010,585,667Method and system to provide user-level multithreading202010,459,858Programmable event driven yield mechanism which may activate other threads201910,452,403Mechanism for instruction set based thread execution on a plurality of instruction sequencers20199,990,206Mechanism for instruction set based thread execution of a plurality of instruction sequencers20189,952,859Method and system to provide user-level multithreading20189,910,796'Programmable event driven yield mechanism which may activate other threads'20189,875,102Apparatus, system, and method for persistent user-level thread20189,766,891'Apparatus, system, and method for persistent user-level thread'20179,720,697'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'20179,588,771'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20179,459,874'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20169,442,721'Method and system to provide user-level multithreading'20169,383,997'Apparatus, system, and method for persistent user-level thread'20169,189,230'Method and system to provide concurrent user-level, non-privileged shared resource thread creation and execution'20159,069,605'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20158,914,618'Instruction set architecture-based inter-sequencer communications with a heterogeneous resource'20148,887,174'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20148,868,887'Programmable event driven yield mechanism which may activate other threads'20148,839,258'Load balancing for multi-threaded applications via asymmetric power throttling'20148,812,792'Technique for using memory attributes'20148,762,694'Programmable event-driven yield mechanism'20148,760,411'Method for determining the number of fingers on a sensing device'20148,743,061'Touch sensing method and electronic device'20148,719,819'Mechanism for instruction set based thread execution on a plurality of instruction sequencers'20148,719,806'Speculative multi-threading for instruction prefetch and/or trace pre-build'20148,612,949'Methods and apparatuses for compiler-creating helper threads for multi-threading'20138,607,235'Mechanism to schedule threads on OS-sequestered sequencers without operating system intervention'20138,560,781'Technique for using memory attributes'20138,522,220'Post-pass binary adaptation for software-based speculative precomputation'20138,516,483'Transparent support for operating system services for a sequestered sequencer'20138,479,217'Apparatus, system, and method for persistent user-level thread'20138,346,760'Method and apparatus to improve execution of a stored program'20138,332,619'Primitives to enhance thread-level speculation'20128,205,200'Compiler-based scheduling optimization hints for user-level threads'20128,108,863'Load balancing for multi-threaded applications via asymmetric power throttling'20128,095,920'Post-pass binary adaptation for software-based speculative precomputation'20128,078,831'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'20118,079,035'Data structure and management techniques for local user-level thread data'20118,074,274'User-level privilege management'20118,037,465'Thread-data affinity optimization using compiler'20118,028,295'Apparatus, system, and method for persistent user-level thread'20118,019,947'Technique for thread communication and synchronization'20118,010,969'Mechanism for monitoring instruction set based thread execution on a plurality of instruction sequencers'20117,991,965'Technique for using memory attributes'20117,882,339'Primitives to enhance thread-level speculation'20117,882,498'Method, system, and program of a compiler to parallelize source code'20117,849,465'Programmable event driven yield mechanism which may activate service threads'20107,844,801'Method and apparatus for affinity-guided speculative helper threads in chip multiprocessors'20107,818,547'Method and apparatus for efficient resource utilization for prescient instruction prefetch'20107,814,469'Speculative multi-threading for instruction prefetch and/or trace pre-build'20107,810,083'Mechanism to emulate user-level multithreading on an OS-sequestered sequencer'20107,743,233'Sequencer address management'20107,657,880'Safe store for speculative helper threads'20107,631,307'User-programmable low-overhead multithreading'20097,603,546'System, method and apparatus for dependency chain processing'20097,587,584'Mechanism to exploit synchronization overhead to improve multithreaded performance'20097,580,914'Method and apparatus to improve execution of a stored program'20097,523,465'Methods and apparatus for generating speculative helper thread spawn-target points'20097,487,502'Programmable event driven yield mechanism which may activate other threads'20097,487,341'Handling address translations and exceptions of a heterogeneous resource of a processor using another processor resource'20097,437,581'Method and apparatus for varying energy per instruction according to the amount of available parallelism'20087,424,576'Parallel cachelets'20087,404,067'Method and apparatus for efficient utilization for prescient instruction prefetch'20087,398,521'Methods and apparatuses for thread management of multi-threading'20087,363,467'Dependence-chain processing using trace descriptors having dependency descriptors'20087,328,433'Methods and apparatus for reducing memory latency in a software application'20087,260,705'Apparatus to implement mesocode'20077,228,528'Building inter-block streams from a dynamic execution trace for a program'20077,216,201'Parallel cachelets'20077,120,749'Cache mechanism'20067,069,545'Quantization and compression for computation reuse'20067,051,193'Register rotation prediction and precomputation'20066,954,848'Marking in history table instructions slowable/delayable for subsequent executions when result is not used immediately'20056,938,126'Cache-line reuse-buffer'20056,928,645'Software-based speculative pre-computation and multithreading'20056,668,306'Non-vital loads'20034,602,210'Multiplexed-access scan testable integrated circuit'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986Based in Oakmont, PA, US· patent location history
2003–2020Patents assigned to INTEL CORP (78)· patent assignee history
2003–2020Based in San Jose, CA, US· patent location history
2011–2017Patents assigned to WANG HONG (23)· patent assignee history
2011–2017Patents assigned to SHEN JOHN (13)· patent assignee history
2011–2015Patents assigned to SHEN JOHN P (12)· patent assignee history
2011–2017Patents assigned to CHINYA GAUTHAM (10)· patent assignee history
2014Based in Tainan, TW· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INTEL CORP | 78 | 2003–2020 |
| WANG HONG | 23 | 2011–2017 |
| SHEN JOHNself | 13 | 2011–2017 |
| SHEN JOHN Pself | 12 | 2011–2015 |
| CHINYA GAUTHAM | 10 | 2011–2017 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 78 | 2003–2020 |
| Tainan, TW | 2 | 2014 |
| Oakmont, Pennsylvania, US | 1 | 1986 |