Inventor
Jochen Supper
Inventor
Herrenberg, DE
Overview
Patents· 19 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Wprimary
H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1027%
G06FElectric digital data processing21%
G01RMeasuring electric variables15%
G02BOptical elements, systems or apparatus15%
H01LSemiconductor devices6%
Y10TTechnical subjects covered by former us classification6%
H03HImpedance networks, e.g. resonant circuits3%
H04LTransmission of digital information, e.g. telegraphic communication3%
H10DInorganic electric semiconductor devices3%
PatentTitleYear
10,461,715Mitigating power noise using a current supply20199,709,625'Measuring power consumption in an integrated circuit'20179,337,122'Transferring heat through an optical layer of integrated circuitry'20169,094,306'Network power fault detection'20159,064,080'Transferring heat through an optical layer of integrated circuitry'20159,058,461'Transferring heat through an optical layer of integrated circuitry'20158,989,532'Integrated circuit package connected to an optical data transmission medium using a coolant'20158,805,132'Integrated circuit package connected to a data transmission medium'20148,659,310'Method and system for performing self-tests in an electronic system'20148,519,720'Method and system for impedance measurement in an integrated Circuit'20138,476,112'Optimized semiconductor packaging in a three-dimensional stack'20138,427,833'Thermal power plane for integrated circuits'20138,405,998'Heat sink integrated power delivery and distribution for integrated circuits'20138,253,234'Optimized semiconductor packaging in a three-dimensional stack'20127,302,664'System and method for automatic insertion of on-chip decoupling capacitors'20077,266,788'Via/BSM pattern optimization to reduce DC gradients and pin current density on single and multi-chip modules'20076,665,843'Method and system for quantifying the integrity of an on-chip power supply network'20036,535,075'Tunable on-chip capacity'20036,424,058'Testable on-chip capacity'2002Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2002–2019Patents assigned to IBM (18)· patent assignee history
2002–2016Based in Herrenberg, DE· patent location history
2003–2019Based in Nufringen, DE· patent location history
2012–2017Patents assigned to SUPPER JOCHEN (10)· patent assignee history
2012–2015Patents assigned to BAROWSKI HARRY (7)· patent assignee history
2012–2015Patents assigned to BRUNSCHWILER THOMAS (7)· patent assignee history
2012–2015Patents assigned to HARRER HUBERT (7)· patent assignee history
2014–2017Based in Boeblingen, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| IBM | 18 | 2002–2019 |
| SUPPER JOCHENself | 10 | 2012–2017 |
| BAROWSKI HARRY | 7 | 2012–2015 |
| BRUNSCHWILER THOMAS | 7 | 2012–2015 |
| HARRER HUBERT | 7 | 2012–2015 |
Locations
| Location | Patents | Span |
|---|---|---|
| Herrenberg, DE | 14 | 2002–2016 |
| Boeblingen, DE | 3 | 2014–2017 |
| Nufringen, DE | 2 | 2003–2019 |