Inventor
Wayne A. Michaelson
Inventor
Circle Pines, MN, US
Overview
Patents· 24 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing88%
G11CStatic stores8%
H03KPulse technique4%
PatentTitleYear
5,649,096'Bus request error detection'19975,612,965'Multiple memory bit/chip failure detection'19975,555,391'System and method for storing partial blocks of file data in a file cache system by merging partial updated blocks with file block to be written'19965,539,888'System and method for processing external conditional branch instructions'19965,535,405'Microsequencer bus controller system'19965,519,876'Processor communications bus having address lines selecting different storage locations based on selected control lines'19965,515,507'Multiple width data bus for a microsequencer bus controller system'19965,495,598'Stuck fault detection for branch instruction condition signals'19965,488,702'Data block check sequence generation and validation in a file cache system'19965,487,159'System for processing shift, mask, and merge operations in one instruction'19965,471,597'System and method for executing branch instructions wherein branch target addresses are dynamically selectable under programmer control from writable branch address tables'19955,453,999'Address verification system using parity for transmitting and receiving circuits'19955,440,604'Counter malfunction detection using prior, current and predicted parity'19955,423,030'Bus station abort detection'19955,257,382'Data bank priority system'19935,060,145'Memory access system for pipelined data paths to and from storage'19915,032,984'Data bank priority system'19914,953,167'Data bus enable verification logic'19904,947,393'Activity verification system for memory or logic'19904,933,908'Fault detection in memory refreshing system'19904,926,313'Bifurcated register priority system'19904,674,032'High-performance pipelined stack with over-write protection'19874,600,986'Pipelined split stack with high performance interleaved decode'19864,590,586'Forced clear of a memory time-out to a maintenance exerciser'1986Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
1986Patents assigned to SPERRY CORP (2)· patent assignee history
1986–1987Based in Lake Elmo, MN, US· patent location history
1987–1997Patents assigned to UNISYS CORP (22)· patent assignee history
1990–1997Based in Circle Pines, MN, US· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| UNISYS CORP | 22 | 1987–1997 |
| SPERRY CORP | 2 | 1986 |
Locations
| Location | Patents | Span |
|---|---|---|
| Circle Pines, Minnesota, US | 21 | 1990–1997 |
| Lake Elmo, Minnesota, US | 3 | 1986–1987 |