Inventor
Thomas J. Giovannini
Inventor
San Jose, CA, US
Overview
Patents· 35 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
G06Fprimary
G06FElectric digital data processing41%
G11CStatic stores41%
Y02DClimate change mitigation technologies in information and communication technologies [ict], i.e. information and communication technologies aiming at the reduction of their own energy use5%
H04BTransmission3%
H01JElectric discharge tubes or discharge lamps2%
H01LSemiconductor devices2%
H03FAmplifiers2%
H03KPulse technique2%
H03MCoding2%
H04LTransmission of digital information, e.g. telegraphic communication2%
PatentTitleYear
11,127,444Signal receiver with skew-tolerant strobe gating202111,068,161Memory module with emulated memory device population202111,016,837Memory module register access202111,003,601Memory system design using buffer(s) on a mother board202110,970,240Protocol including a command-specified timing reference signal202110,846,252Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules202010,789,185Memory modules and systems with variable-width data ranks and configurable data-rank timing202010,614,002Memory system design using buffer(S) on a mother board202010,613,995Training and operations with a double buffered memory topology202010,607,685Method and apparatus for calibrating write timing in a memory system202010,607,670Memory components and controllers that calibrate multiphase synchronous timing references202010,360,972Memories and memory components with interconnected and redundant data interfaces201910,331,587Memory controller that uses a specific timing reference signal in connection with a data burst following a specified idle period201910,320,591Burst-tolerant decision feedback equalization201910,304,517Method and apparatus for calibrating write timing in a memory system201910,223,309Dynamic random access memory (DRAM) component for high-performance, high-capacity registered memory modules201910,169,258Memory system design using buffer(s) on a mother board201910,146,608Memory module register access201810,109,324Extended capacity memory module with dynamic data buffers20189,916,873'Extended capacity memory module with dynamic data buffers'20189,881,662'Method and apparatus for calibrating write timing in a memory system'20189,824,730'Memory components and controllers that calibrate multiphase synchronous timing references'20179,665,507'Protocol including a command-specified timing reference signal'20179,552,865'Method and apparatus for calibrating write timing in a memory system'20179,412,428'Memory components and controllers that calibrate multiphase synchronous timing references'20169,389,637'Methods and systems for recovering intermittent timing-reference signals'20169,298,228'Memory capacity expansion using a memory riser'20169,263,103'Method and apparatus for calibrating write timing in a memory system'20169,177,632'Method and apparatus for calibrating write timing in a memory system'20159,165,638'Method and apparatus for calibrating write timing in a memory system'20159,142,281'Method and apparatus for calibrating write timing in a memory system'20159,141,472'Sharing a check bit memory device between groups of memory devices'20158,407,441'Method and apparatus for calibrating write timing in a memory system'20137,729,621'Controlling a bias voltage for a Mach-Zehnder modulator'20107,297,922'Optical receiver protection circuit'2007Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2007–2021Based in San Jose, CA, US· patent location history
2013–2021Patents assigned to RAMBUS INC (33)· patent assignee history
2013–2017Patents assigned to SHAEFFER IAN (6)· patent assignee history
2013–2017Patents assigned to GIOVANNINI THOMAS J (5)· patent assignee history
2013–2016Patents assigned to GUPTA ALOK (3)· patent assignee history
2013–2016Patents assigned to WOO STEVEN C (3)· patent assignee history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| RAMBUS INC | 33 | 2013–2021 |
| SHAEFFER IAN | 6 | 2013–2017 |
| GIOVANNINI THOMAS Jself | 5 | 2013–2017 |
| GUPTA ALOK | 3 | 2013–2016 |
| WOO STEVEN C | 3 | 2013–2016 |
Locations
| Location | Patents | Span |
|---|---|---|
| San Jose, California, US | 35 | 2007–2021 |