Inventor

CHANRO PARK

Inventor

US

Overview

2021–2026

Patent span

Electricity

Primary field (CPC H)

Patents· 136 as inventor

Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.

H01Lprimary

H01LSemiconductor devices29%

H10DInorganic electric semiconductor devices21%

H10WGeneric packages, interconnections, connectors or other constructional details of devices covered by class h1019%

H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1010%

B82YSpecific uses or applications of nanostructures10%

H10BElectronic memory devices5%

H10NElectric solid-state devices not otherwise provided for3%

G11CStatic stores1%

G03FPhotomechanical production of textured or patterned surfaces, e.g. for printing, for processing of semiconductor devices1%

H01SDevices using the process of light amplification by stimulated emission of radiation [laser] to amplify or generate light1%

PatentTitleYear

12,593,457Multi-state ferroelectric-RAM with stacked capacitors2026 12,588,273Stacked electronic devices having independent gates2026 12,575,160Backside and frontside contacts for semiconductor device2026 12,557,359Self-aligned backside contact with protruding source/drain2026 12,557,356Semiconductor structure with fully wrapped-around backside contact2026 12,557,295Embedded ReRAM with backside contact2026 12,550,427Vertical inverter formation on stacked field effect transistor (SFET)2026 12,550,376Work function metal patterning and middle-of-line self-aligned contacts for nanosheet technology2026 12,550,338Three dimensional cross-point non-volatile memory2026 12,550,708Top via interconnect with an embedded antifuse2026 12,538,785Fully-aligned and dielectric damage-less top via interconnect structure2026 12,525,529Forming line end vias2026 12,500,183Support dielectric fin to prevent gate flop-over in nanosheet transistors2025 12,501,698Stacked transistors having self aligned backside contact with backside replacement metal gate2025 12,495,587Self-aligned contact (SAC) in nanosheet transistors2025 12,489,053Interconnect structure including patterned metal lines2025 12,476,136Liner-less via contact2025 12,453,176Heterogeneous gate all around dielectric thickness2025 12,446,293Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor2025 12,446,480Top contact on resistive random access memory2025 12,439,672Semiconductor backside contact structure with increased contact area2025 12,439,631Non-self-aligned wrap-around contact in a tight gate pitched transistor2025 12,438,047Double patterning with selectively deposited spacer2025 12,426,338Buried power rail with robust connection to a wrap around contact2025 12,417,944Formation of trench silicide source or drain contacts without gate damage2025 12,419,080Semiconductor structure with wrapped-around backside contact2025 12,406,920Top via interconnect with airgap2025 12,400,912Dual-damascene fav interconnects with dielectric plug2025 12,402,329Top via containing random-access memory cross-bar array2025 12,396,225Method to release nano sheet after nano sheet fin recess2025 12,389,609Circuit architecture using transistors with dynamic dual functionality for logic and embedded memory drivers2025 12,389,813Resistive switching memory cell2025 12,382,662Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors2025 12,382,708Vertical stacked nanosheet CMOS transistors with different work function metals2025 12,382,665Increased gate length at given footprint for nanosheet device2025 12,369,494MRAM top electrode structure with liner layer2025 12,362,004Scaled 2T DRAM2025 12,356,638Metal-insulator-metal capacitor structure with enlarged capacitor area2025 12,341,100Copper interconnects with self-aligned hourglass-shaped metal cap2025 12,336,279Fin stack including tensile-strained and compressively strained fin portions2025 12,328,916CPP-agnostic source-drain contact formation for gate-all-around devices with dielectric isolation2025 12,324,197Spin-based gate-all-around transistors2025 12,324,234Fork sheet device with better electrostatic control2025 12,317,514Resistive random-access memory structures with stacked transistors2025 12,315,807Reducing copper line resistance2025 12,310,061Nanosheet transistor devices with different active channel widths2025 12,310,064Isolation pillar structures for stacked device structures2025 12,261,056Top via patterning using metal as hard mask and via conductor2025 12,243,770Hard mask removal without damaging top epitaxial layer2025 12,224,203Air gap spacer formation for nano-scale semiconductor devices2025 12,211,848Field effect transistors comprising a matrix of gate-all-around channels2025 12,183,740Stacked field-effect transistors2024 12,176,345Stacked FET with independent gate control2024 12,148,617Structure and method to pattern pitch lines2024 12,150,310Ferroelectric random-access memory cell2024 12,142,562Subtractive metal etch with improved isolation for BEOL interconnect and cross point2024 12,107,014Nanosheet transistors with self-aligned gate cut2024 12,094,949Fin-type field effect transistor having a wrap-around gate with bottom isolation and inner spacers to reduce parasitic capacitance2024 12,094,972Gate-all-around field effect transistors having end portions of nanosheet channel layers adjacent to source/drain regions being wider than the center portions2024 12,087,624Beol tip-to-tip shorting and time dependent dielectric breakdown2024 12,062,609Electronic fuse structure embedded in top via2024 12,057,395Top via interconnects without barrier metal between via and above line2024 12,046,643Semiconductor structures with power rail disposed under active gate2024 12,027,416BEOL etch stop layer without capacitance penalty2024 12,009,422Self aligned top contact for vertical transistor2024 12,004,435Tunable resistive random access memory cell2024 12,004,436RRAM with high work function cap2024 12,002,850Nanosheet-based semiconductor structure with dielectric pillar2024 11,972,977Fabrication of rigid close-pitch interconnects2024 11,955,526Thick gate oxide device option for nanosheet device2024 11,942,374Nanosheet field effect transistor with a source drain epitaxy replacement2024 11,935,930Wrap-around-contact for 2D-channel gate-all-around field-effect-transistors2024 11,937,521Structure and method to fabricate resistive memory with vertical pre-determined filament2024 11,923,363Semiconductor structure having bottom isolation and enhanced carrier mobility2024 11,923,246Via CD controllable top via structure2024 11,916,073Stacked complementary field effect transistors2024 11,916,013Via interconnects including super vias2024 11,908,732Alternating spacers for pitch structure2024 11,895,934Phase change memory with heater2024 11,882,772Conductive-bridging semiconductor memory device formed by selective deposition2024 11,881,431Anti-fuse with laterally extended liner2024 11,876,114Airgap gate spacer2024 11,848,384Semiconductor device with airgap spacer formation from backside of wafer2023 11,848,264Semiconductor structure with stacked vias having dome-shaped tips2023 11,798,842Line formation with cut-first tip definition2023 11,791,396Field effect transistor with multiple gate dielectrics and dual work-functions with precisely controlled gate lengths2023 11,784,125Wrap around cross-couple contact structure with enhanced gate contact size2023 11,777,275Augmented semiconductor lasers with spontaneous emissions blockage2023 11,742,350Metal gate N/P boundary control by active gate cut and recess2023 11,735,475Removal of barrier and liner layers from a bottom of a via2023 11,735,590Fin stack including tensile-strained and compressively strained fin portions2023 11,728,433Vertical transistor with self-aligned gate2023 11,688,646Reduced source/drain coupling for CFET2023 11,658,062Air gap spacer formation for nano-scale semiconductor devices2023 11,637,179Airgap vertical transistor without structural collapse2023 11,637,238Resistive random-access memory cell and manufacturing method thereof2023 11,631,617Scalable device for FINFET technology2023 11,626,287Semiconductor device with improved contact resistance and via connectivity2023 11,569,361Nanosheet transistors with wrap around contact2023 11,527,535Variable sheet forkFET device2022 11,476,163Confined gate recessing for vertical transport field effect transistors2022 11,456,181Cross-bar fin formation2022 11,443,982Formation of trench silicide source or drain contacts without gate damage2022 11,437,489Techniques for forming replacement metal gate for VFET2022 11,410,879Subtractive back-end-of-line vias2022 11,380,581Interconnect structures of semiconductor devices having a via structure through an upper conductive line2022 11,328,954Bi metal subtractive etch for trench and via formation2022 11,315,872Self-aligned top via2022 11,315,799Back end of line structures with metal lines with alternating patterning and metallization schemes2022 11,309,220Methods, apparatus, and manufacturing system for self-aligned patterning of a vertical transistor2022 11,289,375Fully aligned interconnects with selective area deposition2022 11,282,838Stacked gate structures2022 11,270,913BEOL metallization formation2022 11,264,481Self-aligned source and drain contacts2022 11,257,718Contact structures2022 11,244,897Back end of line metallization2022 11,244,854Dual damascene fully aligned via in interconnects2022 11,244,853Fully aligned via interconnects with partially removed etch stop layer2022 11,211,452Transistor having stacked source/drain regions with formation assistance regions and multi-region wrap-around source/drain contacts2021 11,211,462Using selectively formed cap layers to form self-aligned contacts to source/drain regions2021 11,205,591Top via interconnect with self-aligned barrier layer2021 11,201,056Pitch multiplication with high pattern fidelity2021 11,201,112Fully-aligned skip-vias2021 11,183,581Vertical field effect transistor having improved uniformity2021 11,183,561Nanosheet transistor with inner spacers2021 11,177,632Augmented semiconductor lasers with spontaneous emissions blockage2021 11,177,163Top via structure with enlarged contact area with upper metallization level2021 11,177,170Removal of barrier and liner layers from a bottom of a via2021 11,177,214Interconnects with hybrid metal conductors2021 11,177,181Scalable device for FINFET technology2021 11,171,044Planarization controllability for interconnect structures2021 11,164,774Interconnects with spacer structure for forming air-gaps2021 11,164,793Reduced source/drain coupling for CFET2021 11,158,544Vertical stacked nanosheet CMOS transistors with different work function metals2021 11,139,399Vertical transistor with self-aligned gate2021 11,139,202Fully aligned top vias with replacement metal lines2021

Career & activity timeline

Assembled from patent assignee/location history and declaration credentials.

2021–2026Patents assigned to IBM (129)· patent assignee history

2021–2026Based in US· patent location history

2022–2025Patents assigned to GLOBALFOUNDRIES US INC (4)· patent assignee history

2022Patents assigned to GLOBALFOUNDRIES INC (1)· patent assignee history

2023Patents assigned to TESSERA LLC (1)· patent assignee history

2025Patents assigned to ADEIA SEMICONDUCTOR SOLUTIONS LLC (1)· patent assignee history

Inventor activity

Assignee and location history derived from the patent record.

Assignees

Assignee	Patents	Span
IBM	129	2021–2026
GLOBALFOUNDRIES US INC	4	2022–2025
ADEIA SEMICONDUCTOR SOLUTIONS LLC	1	2025
GLOBALFOUNDRIES INC	1	2022
TESSERA LLC	1	2023

Locations

Location	Patents	Span
US	136	2021–2026