Inventor
Susanne Lachenmann
Inventor
Munich, DE
Overview
Patents· 4 as inventor
Public. Assignee & technology derived from the patent record. Each patent links to its LexDana page.
H10Pprimary
H10PGeneric processes or apparatus for the manufacture or treatment of devices covered by class h1040%
H10BElectronic memory devices30%
G11CStatic stores20%
Y10STechnical subjects covered by former uspc cross-reference art collections [xracs] and digests10%
PatentTitleYear
7,372,072'Semiconductor wafer with test structure'20087,205,567'Semiconductor product having a semiconductor substrate and a test structure and method'20077,126,154'Test structure for a single-sided buried strap DRAM memory cell array'20066,856,562'Test structure for measuring a junction resistance in a DRAM memory cell array'2005Career & activity timeline
Assembled from patent assignee/location history and declaration credentials.
2005–2008Patents assigned to INFINEON TECHNOLOGIES AG (4)· patent assignee history
2005–2006Based in München, DE· patent location history
2007–2008Based in Munich, DE· patent location history
Inventor activity
Assignee and location history derived from the patent record.
Assignees
| Assignee | Patents | Span |
|---|---|---|
| INFINEON TECHNOLOGIES AG | 4 | 2005–2008 |
Locations
| Location | Patents | Span |
|---|---|---|
| Munich, DE | 2 | 2007–2008 |
| München, DE | 2 | 2005–2006 |